The rapid increase in the number of cores on chips forced the designers to invent new communication methods such as Network-on-Chip (NoC) paradigm. Advances in integrated circuit fabrications even allowed three-dimensional NoC (3D-NoC) implementations. 3D-NoCs have more advantages than their 2D counterparts such as lower area, higher throughput, better performance, and less energy consumption. However, they lack the design automation algorithms. An important design problem for a given application is mapping it on a 3D-NoC topology. In this paper, we present an integer linear programming (ILP) formulation and a novel heuristic algorithm, called CastNet3D, for application mapping onto mesh-based 3D-NoCs with energy minimization being the objective. The algorithm tries to utilize vertical links for communicating nodes as much as possible. Vertical links are shorter than horizontal ones; therefore, they are faster and consume less energy. We compared CastNet3D against ILP in terms of energy consumption and execution time on several benchmarks. Our results show that CastNet3D obtains close to optimum results in much shorter time frames.
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International Technology Roadmap for Semiconductors (ITRS) Report 2015, http://www.itrs2.net/
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This work was supported by The Scientific and Technological Research Council of Turkey (TUBITAK) under Grant No. 117E130.
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Nalci, Y., Kullu, P., Tosun, S. et al. ILP formulation and heuristic method for energy-aware application mapping on 3D-NoCs. J Supercomput (2020). https://doi.org/10.1007/s11227-020-03365-0