ILP formulation and heuristic method for energy-aware application mapping on 3D-NoCs


The rapid increase in the number of cores on chips forced the designers to invent new communication methods such as Network-on-Chip (NoC) paradigm. Advances in integrated circuit fabrications even allowed three-dimensional NoC (3D-NoC) implementations. 3D-NoCs have more advantages than their 2D counterparts such as lower area, higher throughput, better performance, and less energy consumption. However, they lack the design automation algorithms. An important design problem for a given application is mapping it on a 3D-NoC topology. In this paper, we present an integer linear programming (ILP) formulation and a novel heuristic algorithm, called CastNet3D, for application mapping onto mesh-based 3D-NoCs with energy minimization being the objective. The algorithm tries to utilize vertical links for communicating nodes as much as possible. Vertical links are shorter than horizontal ones; therefore, they are faster and consume less energy. We compared CastNet3D against ILP in terms of energy consumption and execution time on several benchmarks. Our results show that CastNet3D obtains close to optimum results in much shorter time frames.

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  1. 1.

    International Technology Roadmap for Semiconductors (ITRS) Report 2015,

  2. 2.

    Dally WJ, Towles B (2001) Route packets, not wires: on-chip inteconnection networks. In: Proceedings of the 38th Annual Design Automation Conference, pp 684–689

  3. 3.

    Sheibanyrad A, Pétrot F, Jantsch A (2011) 3D integration for NoC-based SoC architectures. Springer, Berlin

    Google Scholar 

  4. 4.

    Van der Plas G et al (2011) Design issues and considerations for low-cost 3-D TSV IC technology. IEEE J Solid-State Circ 46(1):293–307

    Article  Google Scholar 

  5. 5.

    Tosun S, Ozturk O, Ozen M (2009, October) An ILP formulation for application mapping onto network-on-chips. In: 2009 International Conference on Application of Information and Communication Technologies, pp 1–5. IEEE

  6. 6.

    Tosun S (2011) New heuristic algorithms for energy aware application mapping and routing on mesh-based NoCs. J Syst Architect 57(1):69–78

    Article  Google Scholar 

  7. 7.

    Sahu PK, Shah T, Manna K, Chattopadhyay S (2014) Application mapping onto mesh-based network-on-chip using discrete particle swarm optimization. IEEE Trans Very Large Scale Integr Syst 22(2):300–312

    Article  Google Scholar 

  8. 8.

    Huang C, Zhang D, Song G (2017) A novel mapping algorithm for three-dimensional network on chip based on quantum-behaved particle swarm optimization. Front Comput Sci 11(4):622–631

    Article  Google Scholar 

  9. 9.

    Fang J, Yu T, Wei Z (2020) Improved ant colony algorithm based on task scale in network on chip (NoC) mapping. Electronics 9(1):6

    Article  Google Scholar 

  10. 10.

    Fen G, Gui F, Shuang Y, Ning W (2013) Power-and thermal-aware mapping for 3D network-on-chip. Inf Technol J 12(23):7297–7304

    Article  Google Scholar 

  11. 11.

    Dageleh MZ, Jamali MAJ (2018) V-CastNet3D: a novel clustering-based mapping in 3-D network on chip. Nano Commun Netw 18:51–61

    Article  Google Scholar 

  12. 12.

    Wang J, Li L, Pan H, He S, Zhang R (2011) Latency-aware mapping for 3D NoC using rank-based multi-objective genetic algorithm. In: 2011 9th IEEE International Conference on ASIC, pp 413–416

  13. 13.

    Elmiligi H, Gebali F, El-Kharashi MW (2014) Power-aware mapping for 3D-NoC designs using genetic algorithms. Procedia Comput Sci 34:538–543

    Article  Google Scholar 

  14. 14.

    Manna K, Swami S, Chattopadhyay S, Sengupta I (2016) Integrated through-silicon via placement and application mapping for 3D mesh-based NoC design. ACM Trans Embedd Comput Syst 16(1):24

    Article  Google Scholar 

  15. 15.

    Hu J, Marculescu R (2003) Exploiting the routing flexibility for energy/performance aware mapping of regular NoC architectures. In: 2003 Design, Automation and Test in Europe Conference and Exhibition, pp 688–693

  16. 16.

    Tosun S, Ajabshir VB (2018) Energy-aware partitioning of fault-tolerant irregular topologies for 3D network-on-chips. J Supercomput 74(9):4842–4863

    Article  Google Scholar 

  17. 17.

  18. 18.

    Tosun S, Ozturk O, Ozkan E, Ozen M (2015) Application mapping algorithms for mesh-based network-on-chip architectures. J Supercomput 71(3):995–1017

    Article  Google Scholar 

  19. 19.

    Janidarmian M, Khademzadeh A, Tavanpour M (2009) Onyx: a new heuristic bandwidth-constrained mapping of cores onto tile-based Network on Chip. IEICE Electron Express 6(1):1–7

    Article  Google Scholar 

  20. 20.

    Srinivasan K, Chatha KS, Konjevod G (2006) Linear-programming-based techniques for synthesis of network-on-chip architectures. IEEE Trans Very Large Scale Integr Syst 14(4):407–420

    Article  Google Scholar 

  21. 21.

    Qian Z, Bogdan P, Tsui CY, Marculescu R (2016) Performance evaluation of noc-based multicore systems: From traffic analysis to noc latency modeling. ACM Trans Des Autom Electron Syst 21(3):52

    Article  Google Scholar 

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This work was supported by The Scientific and Technological Research Council of Turkey (TUBITAK) under Grant No. 117E130.

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Correspondence to Pinar Kullu.

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Nalci, Y., Kullu, P., Tosun, S. et al. ILP formulation and heuristic method for energy-aware application mapping on 3D-NoCs. J Supercomput (2020).

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  • 3D-mesh
  • ILP
  • Mapping