Advertisement

The Journal of Supercomputing

, Volume 74, Issue 4, pp 1676–1694 | Cite as

Privatizing transactions for Lee’s algorithm in commercial hardware transactional memory

  • Ricardo Quislant
  • Eladio Gutierrez
  • Emilio L. Zapata
  • Oscar Plata
Article
  • 77 Downloads

Abstract

Lee’s algorithm solves the path-connection problems that arise in logical drawing, wiring diagramming or optimal route finding. Its parallel version has been widely used as a benchmark to test transactional memory systems. It exhibits transactions of large size and duration that stress these systems exposing their limitations. In fact, Lee’s algorithm has been proved to perform similar to sequential in commercial hardware transactional memory systems due to persistent capacity overflows. In this paper, we propose a novel approach to Lee’s algorithm in the context of commercial hardware transactional memory systems. We show how the majority of the computation of the largest transaction, i.e. grid privatization and path calculation, can be executed out of the boundaries of the transaction, thus reducing the size requirements. We leverage the correctness criteria of lazy subscription fallback locks to ensure a correct execution. This novel approach uses transactional memory extensions from commercial processors from a different point of view, not needing either early release or open-nested transaction features that are not yet implemented in these systems. We propose an application programming interface to facilitate the task of the programmer. Experiments are carried out with the Intel Core and IBM Power8 architectures, showing speedups around 3.5\(\times \) over both the standard transactional version of the algorithm and the sequential for certain grid inputs and four threads. We also compare our proposal with a software transactional memory LeeTM approach.

Keywords

Hardware transactional memory Lee’s algorithm Early release Open transactions Lazy subscription 

Notes

Acknowledgements

This work has been supported by the Government of Spain under project TIN2013-42253-P and TIN2016-80920-R, and Junta de Andalucía under project P12-TIC-1470.

References

  1. 1.
    Herlihy M, Moss J (1993) Transactional memory: architectural support for lock-free data structures. In: 20th Annual International Symposium on Computer Architecture (ISCA’93), pp 289–300Google Scholar
  2. 2.
    Yoo RM, Hughes CJ, Lai K, Rajwar R (2013) Performance evaluation of intel transactional synchronization extensions for high-performance computing. In: International Conference on High Performance Computing, Networking, Storage and Analysis (SC’13), pp 19:1–19:11Google Scholar
  3. 3.
    Cain HW, Michael MM, Frey B, May C, Williams D, Le H (2013) Robust architectural support for transactional memory in the power architecture. In: 40th Annual International Symposium on Computer Architecture (ISCA’13), pp 225–236Google Scholar
  4. 4.
    Minh C, Chung J, Kozyrakis C, Olukotun K (2008) STAMP: stanford transactional applications for multi-processing. In: IEEE Internationall Symposium on Workload Characterization (IISWC’08), pp 35–46Google Scholar
  5. 5.
    Lee CY (1961) An algorithm for path connections and its applications. IRE Trans Electron Comput EC–10(3):346–365MathSciNetCrossRefGoogle Scholar
  6. 6.
    Schindewolf M, Bihari B, Gyllenhaal J, Schulz M, Wang A, Karl W (2012) What scientific applications can benefit from hardware transactional memory? In: International Conference on High Performance Computing, Networking, Storage and Analysis (SC’12), p 90:1–90:11Google Scholar
  7. 7.
    Goel B, Titos-Gil R, Negi A, Mckee SA, Stenstrom P (2014) Performance and energy analysis of the restricted transactional memory implementation on Haswell. In: 28th International Symposium on Parallel and Distributed Processing (IPDPS’14), pp 615–624Google Scholar
  8. 8.
    Machado Pereira M, Gaudet M, Nelson Amaral J, Araujo G (2016) Study of hardware transactional memory characteristics and serialization policies on Haswell. Parallel Comput 54:46–58MathSciNetCrossRefGoogle Scholar
  9. 9.
    Nakaike T, Odaira R, Gaudet M, Michael MM, Tomari H (2015) Quantitative comparison of hardware transactional memory for Blue Gene/Q, zEnterprise EC12, Intel Core, and POWER8. In: 42nd Annual International Symposium on Computer Architecture (ISCA’15), pp 144–157Google Scholar
  10. 10.
    Ansari M (2014) Weighted adaptive concurrency control for software transactional memory. J Supercomput 68(3):1027–1047CrossRefGoogle Scholar
  11. 11.
    Atoofian E (2013) Improving performance of software transactional memory through contention locality. J Supercomput 64(2):527–547CrossRefGoogle Scholar
  12. 12.
    Chen CJ, Chang RG (2015) A priority scheduling for tm pathologies. J Supercomput 71(3):1095–1115CrossRefGoogle Scholar
  13. 13.
    Harvey HH, Mao Y, Hou Y, Sheng B (2017) EDOS: Edge assisted offloading system for mobile devices. In: International Conference on Computer Communication and Networks (ICCCN’17), pp 1–9Google Scholar
  14. 14.
    Calciu I, Shpeisman T, Pokam G, Herlihy M (2014) Improved single global lock fallback for best-effort hardware transactional memory. In: 9th workshop on transactional computing (TRANSACT’14)Google Scholar
  15. 15.
    Herlihy M, Luchangco V, Moir M, Scherer III, WN (2003) Software transactional memory for dynamic-sized data structures. In: 22nd annual symposium on principles of distributed computing (PODC ’03), pp 92–101Google Scholar
  16. 16.
    Moravan MJ, Bobba J, Moore KE, Yen L, Hill MD, Liblit B, Swift MM, Wood DA (2006) Supporting nested transactional memory in logTM. In: 12th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS’06), pp 359–370Google Scholar
  17. 17.
    Won Y, Sahni S (1988) Maze routing on a hypercube multicomputer. J Supercomput 2(1):55–79CrossRefGoogle Scholar
  18. 18.
    Yen IL, Dubash RM, Bastani FB (1993) Strategies for mapping Lee’s maze routing algorithm onto parallel architectures. In: International Parallel Processing Symposium, pp 672–679Google Scholar
  19. 19.
    Watson I, Kirkham C, Lujan M (2007) A study of a transactional parallel routing algorithm. In: 16th International Conference on Parallel Architecture and Compilation Techniques (PACT ’07), pp 388–398Google Scholar
  20. 20.
    Ansari M, Kotselidis C, Watson I, Kirkham C, Luján M, Jarvis K (2008) Lee-TM: a non-trivial benchmark suite for transactional memory, In: International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP’08), pp 196–207Google Scholar
  21. 21.
    Herlihy M, Luchangco V, Moir M (2006) A flexible framework for implementing software transactional memory. In: conference on Object-Oriented Programming Systems, Languages, and Applications (OOPSLA’06), pp 253–262Google Scholar
  22. 22.
    Felber P, Fetzer C, Riegel T (2008) Dynamic performance tuning of word-based software transactional memory. In: Symposium on Principles and Practice of Parallel Programming (PPoPP’08), pp 237–246Google Scholar
  23. 23.
    Quislant R, Gutierrez E, Zapata EL, Plata O (2016) Insights into the fallback path of best-effort hardware transactional memory systems. In: International Conference on Parallel Processing (Euro-Par’16), pp 251–263Google Scholar
  24. 24.
    Martin MMK, Blundell C, Lewis E (2006) Subtleties of transactional memory atomicity semantics. IEEE Comput Archit Lett 5(2):17Google Scholar
  25. 25.
    Dice D, Herlihy M, Lea D, Lev Y, Luchangco V, Mesard W, Moir M, Moore K, Nussbaum D (2008) Applications of the adaptive transactional memory test platform. In: 3rd workshop on transactional computing (TRANSACT’08)Google Scholar
  26. 26.
    Intel: Intel(R) Architecture Instruction Set Extensions Programming Reference. Tech. Rep. February (2012)Google Scholar
  27. 27.
    Dragojevic A TinySTM version of LeeTM. University of Manchester. http://apt.cs.manchester.ac.uk/projects/TM/LeeBenchmark/

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2017

Authors and Affiliations

  1. 1.Department of Computer ArchitectureUniversity of MálagaMálagaSpain

Personalised recommendations