An Efficient, Low-Cost Routing Architecture for Spiking Neural Network Hardware Implementations
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The basic processing units in brain are neurons and synapses that are interconnected in a complex pattern and show many surprised information processing capabilities. The researchers attempt to mimic this efficiency and build artificial neural systems in hardware device to emulate the key information processing principles of the brain. However, the neural network hardware system has a challenge of interconnecting neurons and synapses efficiently. An efficient, low-cost routing architecture (ELRA) is proposed in this paper to provide a communication infrastructure for the hardware spiking neuron networks (SNN). A dynamic traffic arbitration strategy is employed in ELRA, where the traffic status weights of input ports are calculated in real-time according to the channel traffic statuses and the port with the largest traffic status weight is given a high priority to forward packets. This strategy enables the router to serve congested ports preferentially, which can balance the overall network traffic loads. Experimental results show the feasibility of ELRA under various traffic scenarios, and the hardware synthesis result using SAED 90 nm technology demonstrates it has a low hardware area overhead which maintains scalability for large-scale SNN hardware implementations.
KeywordsSpiking neural networks Networks-on-chip Routing arbitration
This research was supported by the National Natural Science Foundation of China under Grants 61603104 and 61661008, the Guangxi Natural Science Foundation under Grants 2015GXNSFBA139256 and 2016GXNSFCA380017, the funding of Overseas 100 Talents Programme of Guangxi Higher Education, the Research Project of Guangxi University of China under Grant KY2016YB059, Guangxi Key Lab of Multi-source Information Mining and Security under Grant MIMS15-07, the Doctoral Research Foundation of Guangxi Normal University, the Research Project of Guangxi Centre of Humanities and Social Sciences—Ecological Environment Forecast and Harnessing in Ecologically Vulnerable Region of Pearl River and Xijiang Economic Zone (ZX2016030), and the Innovation Project of Guangxi Graduate Education (YCSZ2016034).
- 11.Wang R, Hamilton TJ, Tapson J, van Schaik A, Topology A, Dp G (2014) An FPGA design framework for large-scale spiking neural networks. In: IEEE international symposium on circuits and systems, pp 457–460Google Scholar
- 13.Dally WJ, Towles B (2001) Route packets, not wires: on-chip interconnection networks. In: Proceedings of the 38th design automation conference, pp 684–689Google Scholar
- 15.Schemmel J, Fieres J, Meier K (2008) Wafer-scale integration of analog neural networks. In: Proceedings of the international joint conference on neural networks, pp 431–438Google Scholar
- 19.Wan L, Luo Y, Song S, Harkin J, Liu J (2016) Efficient neuron architecture for FPGA-based spiking neural networks. In: Proceedings of the 27th Irish signals and systems conference, pp 1–6Google Scholar
- 20.Luo Y, Fu Q, Liu J, Harkin J, McDaid L, Cao Y (2017) An extended algorithm using adaptation of momentum and learning rate for spiking neurons emitting multiple spikes. In: Proceedings of the international work conference on artificial neural networks, pp 1–11Google Scholar