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Efficient FPGA architecture of optimized Haar wavelet transform for image and video processing applications

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Abstract

Discrete Wavelet Transform (DWT) is widely used in digital image and video processing due to its various advantages over other similar transform techniques. In this paper, efficient hardware architecture of Optimized Haar Wavelet Transform is proposed which is modeled using Optimized Kogge–Stone Adder/Subtractor, Optimized Controller, Buffer, Shifter and D_FF blocks. The existing Kogge–Stone Adder architecture is optimized by using Modified Carry Correction block which uses parallel architecture to reduce the computational delay. Similarly, the Controller block is optimized by using Clock Dividers and Reset Counter interdependently. To preserve the accuracy of the processed data, suitable size of intermediate bits in fractional format with the help of Q-notation is considered. The comparison results show that the proposed architecture performs better than existing ones concerning both hardware utilization and data accuracy.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Vijaya Vittala Institute of Technology, Bangalore, Karnataka, 560077, India

    Sayantam Sarkar

  2. Department of Electronics and Communication Engineering, Shri Dharmasthala Manjunatheshwara College of Engineering and Technology, Dharwad, Karnataka, 580002, India

    Satish S. Bhairannawar

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  1. Sayantam Sarkar
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Appendices

Appendices

The user-defined symbols are used in all the algorithms and equations present in this paper are as follows

  • \({{\sim \,\leftarrow }}\) Logical NOT Operation.

  • \({{| \,\leftarrow }}\) Logical OR Operation.

  • \({{\bigoplus \leftarrow }}\) Logical XOR Operation.

  • \( {{ \& \leftarrow }}\) Logical AND Operation.

  • \({{{(, )}\big /{\{,\}}\big /{[, ]} \leftarrow }}\) Logical Concatenation Operation.

  • \({{(x~downto~y) \leftarrow }}\) Data of Length (x-y+1).

  • \({{(N) \leftarrow }}\) Bit Present in Nth Position of a Binary Digit.

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Sarkar, S., Bhairannawar, S.S. Efficient FPGA architecture of optimized Haar wavelet transform for image and video processing applications. Multidim Syst Sign Process 32, 821–844 (2021). https://doi.org/10.1007/s11045-020-00759-4

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