High speed and low area decision feed-back equalizer with novel memory less distributed arithmetic filter

Abstract

In this paper an efficient implementation of decision feed back equalizer (DFE) is carried out using novel memory less distributed arithmetic (NMLDA) filter. In wireless transmission systems, DFEs are used to mitigate the inter-symbol interference (ISI). The ISI is occurred due to multi-path propagation of the transmitted signal. High data rate systems demand higher order filters in DFE architectures which increase complexity in hardware design. In our proposed NMLDA design, we have used multiplexers and enhanced compressor adders in place of memory unit and conventional adders. The proposed design occupies lower area and gives higher throughput, when compared to MAC based filter and all other memory based DA filter architectures. By using proposed NMLDA based DFE, the ISI errors in transmission signal, will be minimized and the performance of the transmission system will be enhanced. We have synthesized the NMLDA of 32-tap, 16-tap, 8-tap and 4-tap filters and implemented them on FPGA device. The proposed design has nearly 70% less number of logical elements than OBC DA and 50% less than MDA and offers better throughput than the existing designs when implemented on Altera Cyclone III EP3C55F484C6.

This is a preview of subscription content, log in to check access.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11

References

  1. 1.

    Burleson WP, Scharf LL (1991) A vlsi design methodology for distributed arithmetic. Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology 2(4):235–252

    Article  Google Scholar 

  2. 2.

    Callender C, Theodoridis S, Cowan C (1994) Adaptive non-linear equalisation of digital communications channels. Signal Process 40(2-3):325–333

    Article  Google Scholar 

  3. 3.

    Chen HC, Guo JI, Jen CW, Chang TS (2005) Distributed arithmetic realisation of cyclic convolution and its dft application. IEE Proceedings-Circuits Devices and Systems 152(6):615–629

    Article  Google Scholar 

  4. 4.

    Croisier A, Esteban D, Levilion M, Riso V (1973) Digital filter for pcm encoded signals. US Patent 3,777,130

  5. 5.

    Douillard C, Jézéquel M, Berrou C, Electronique D, Picart A, Didier P, Glavieux A (1995) Iterative correction of intersymbol interference: turbo-equalization. Trans Emerg Telecommun Technol 6(5):507–511

    Article  Google Scholar 

  6. 6.

    Ghamkhari SF, MBGG (2012) A low-power, low-area architecture design for distributed arithmetic (da) unit. In: 20th Iranian conference on electrical engineering, vol 1. IEEE, pp i–i

  7. 7.

    Grande NJ, Sridevi S (2017) Asic implementation of shared lut based distributed arithmetic in fir filter. In: 2017 international conference on microelectronic devices, circuits and systems (ICMDCS). IEEE, pp 1–4

  8. 8.

    Hurskainen H, Raasakka J, Ahonen T, Nurmi J (2009) Multicore software-defined radio architecture for gnss receiver signal processing. EURASIP Journal on Embedded Systems 2009(1):543–720

    Google Scholar 

  9. 9.

    Jyothi GN, Sriadibhatla S (2019) Asic implementation of low power, area efficient adaptive fir filter using pipelined da. In: Microelectronics, electromagnetics and telecommunications. Springer, pp 385–394

  10. 10.

    Khan MT, Ahamed SR (2016) Low cost implementation of concurrent decision feedback equalizer using distributed arithmetic. In: 2016 1st India international conference on information processing (IICIP). IEEE, pp 1–5

  11. 11.

    Khan MT, Ahamed SR, Chatterjee A (2016) Efficient implementation of concurrent lookahead decision feedback equalizer using offset binary coding. In: 2016 20th international symposium on VLSI design and test (VDAT). IEEE, pp 1–6

  12. 12.

    Meher PK (2006) Hardware-efficient systolization of da-based calculation of finite digital convolution. IEEE Trans Circuits Syst Express Briefs 53(8):707–711

    Article  Google Scholar 

  13. 13.

    NagaJyothi G, SriDevi S (2017) Distributed arithmetic architectures for fir filters-a comparative review. In: 2017 international conference on wireless communications, signal processing and networking (wiSPNET). IEEE, pp 2684–2690

  14. 14.

    Prakash MS, Shaik R, Koorapati S (2016) An efficient distributed arithmetic-based realization of the decision feedback equalizer. Circuits Systems Signal Process 35(2):603–618

    Article  Google Scholar 

  15. 15.

    Proakis JG (2001) Digital signal processing: principles algorithms and applications. Pearson Education India

  16. 16.

    Qureshi SU (1985) Adaptive equalization. Proc IEEE 73(9):1349–1387

    Article  Google Scholar 

  17. 17.

    Shaik R, Chakraborty M (2006) An efficient realization of the decision feedback equalizer using block floating point arithmetic. In: IEEE Asia Pacific conference on circuits and systems, 2006. APCCAS 2006. IEEE, pp 1047–1050

  18. 18.

    Shaik R, Chakraborty M (2013) A block floating point treatment to finite precision realization of the adaptive decision feedback equalizer. Signal Process 93(5):1162–1171

    Article  Google Scholar 

  19. 19.

    Waelchli G, Baracchi-Frei M, Botteron C, Farine PA (2010) Distributed arithmetic for efficient base-band processing in real-time gnss software receivers. J Electr Comput Eng 2010:2

    Google Scholar 

  20. 20.

    White S (1986) High-speed distributed-arithmetic realization of a second-order normal-form digital filter. IEEE Transactions on Circuits and Systems 33(10):1036–1038

    Article  Google Scholar 

  21. 21.

    White SA (1989) Applications of distributed arithmetic to digital signal processing: a tutorial review. IEEE ASSP Mag 6(3):4–19

    Article  Google Scholar 

  22. 22.

    Yoo H, Anderson DV (2005) Hardware-efficient distributed arithmetic architecture for high-order digital filters. In: IEEE international conference on acoustics, speech, and signal processing, proceedings, vol 5. (ICASSP’05), pp v–125

Download references

Author information

Affiliations

Authors

Corresponding author

Correspondence to Grande NagaJyothi.

Additional information

Publisher’s note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

NagaJyothi, G., Sridevi, S. High speed and low area decision feed-back equalizer with novel memory less distributed arithmetic filter. Multimed Tools Appl 78, 32679–32693 (2019). https://doi.org/10.1007/s11042-018-7038-6

Download citation

Keywords

  • Distributed arithmetic
  • Decision feedback equalizer
  • Non-linear equalizer
  • FIR
  • Feed forward (FF) filter
  • Feed back (FB) filter
  • Linear equalizer
  • Inter symbol interference (ISI)
  • Quantizer