Multimedia Tools and Applications

, Volume 77, Issue 3, pp 3639–3657 | Cite as

Design of reconfigurable array processor for multimedia application

  • Zhu Yun
  • Lin Jiang
  • Shuai Wang
  • Xingjie Huang
  • Hui Song
  • Xueting Li


With the rapid growth of the amount of computations and power consumption, there is a pressing need for a high power-efficiency architecture, which takes account of computational efficiency and flexibility of application. This paper proposes a type of array-processor architecture for multimedia application which is programmable and self-reconfigurable and consists of 1024 thin-core processing elements (PE). The performance and power dissipation are demonstrated with different multimedia application algorithms such as hash, and fractional motion estimation (FME). The results show that the proposed architecture can provide high performance with less energy consumption using parallel computation.


Reconfigurable Array processor Multimedia retrieval Hash Fractional motion estimation (FME) 



This work was supported by the National Natural Science Foundation of China (61272120, 61602377, and 61634004), the Natural Science Foundation of Shaanxi Province of China (2015JM6326), Shaanxi Provincial Co-ordination Innovation Project of Science and Technology (2016KTZDGY02-04-02), and the Project of Education Department of Shaanxi Provincial Government (15JK1683).


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Copyright information

© Springer Science+Business Media, LLC 2017

Authors and Affiliations

  • Zhu Yun
    • 1
  • Lin Jiang
    • 2
  • Shuai Wang
    • 2
  • Xingjie Huang
    • 3
  • Hui Song
    • 2
  • Xueting Li
    • 4
  1. 1.School of microelectronicsXidian UniversityXi’anChina
  2. 2.School of Electronic EngineeringXi’an University of Posts and TelecommunicationsXi’anChina
  3. 3.College of Computer and Information ScienceNortheastern UniversityBostonUSA
  4. 4.School of Computer ScienceXi’an University of Posts and TelecommunicationsXi’anChina

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