Joint application-architeture design space exploration of multimedia applications on many-core platforms - an experimental analysis
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The design space of mapping multimedia applications on an architectural platform is complex and many parameters are needed to be considered in order to find the optimum mapping. Conventionally, architectural parameters are varied to find different design points and the application side parameters are considered fixed and unchanged, while multimedia applications are equipped with several configurations to control the complexity and quality of the output. In this paper, we experimentally investigate joint application-architecture design space exploration of multimedia applications on many-core platforms. The joint exploration is conducted on two state of the art video coding standards and STHorm many-core platform as the underlying architecture. In the first case study, MPEG4-SP decoder is mapped on STHorm with varying buffer size and variable number of Processing Elements (PEs). In the second case study, HEVC (High Efficiency Video Coding) decoder with variable Quantization Parameter (QP) is mapped on STHorm with variable PE number. The application is characterized with representative parameters on the basis of high level dataflow representation of the application. It is demonstrated that joint exploration of these parameters outperforms that of their separate exploration in terms of well-established combinatory metrics such as space-time product and energy-time product metrics while achieving performance constraints.
KeywordsDesign space exploration Energy Execution time Memory Video coding Many-core platform
Part of this research has been conducted in EPFL SCI-STI-MM lab under supervision of Dr. Marco Mattavelli. The authors are grateful for the STHorm platform simulation environment provided by the lab and the application models. Useful discussions, help and support from all the team members are also appreciated heartily by authors.
- 1.“OPEN RVC-CAL Compiler.” [Online]. Available: http://orcc.sourceforge.net/
- 2.Azizi O, Mahesri A, Stevenson JP, Patel SJ, and Horowitz M (2010)“An integrated framework for joint design space exploration of microarchitecture and circuits,” 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), pp. 250–255Google Scholar
- 3.Benini L (2010) Programming heterogeneous many-core platforms in nanometer technology : the P2012 experience. ARTIST DESIGN Summer school Autrans, FranceGoogle Scholar
- 4.Benini L, Flamand E, Fuin D, and Melpignano D (2012) “P2012: Building an ecosystem for a scalable, modular and high-efficiency embedded computing accelerator,” 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp. 983–987Google Scholar
- 6.Brunet SC, Mattavelli M and Janneck JW (2013) “Buffer optimization based on critical path analysis of a dataflow program design,” 2013 I.E. International Symposium on Circuits and Systems (ISCAS2013), pp. 1384–1387Google Scholar
- 9.Helmstetter C (2012) “Guided Tour of the P2012 TLM Model : Simulation Speed and Timing Accuracy,” 19th Open International Workshop on Synchronous Programming, SYNCHRONGoogle Scholar
- 11.Le Beux S, Nicolescu G, Bois G, Bouchebaba Y, Langevin M. , and P. Paulin, “Optimizing Configuration and Application Mapping for MPSoC Architectures,” 2009 NASA/ESA Conference on Adaptive Hardware and Systems, pp. 474–481, Jul. 2009Google Scholar
- 13.Mattavelli M, Amer I, Raulet M (2010) The reconfigurable video coding standard. IEEE Signal Process Mag 27(3):159–165. doi: 10.1109/MSP.2010.936032
- 18.Viitanen M, Vanne J, Hämäläinen TD, Gabbouj M and Lainema J (2013) “Complexity Analysis of Next-Generation HEVC Decoder,” 2012 I.E. International Symposium on Circuits and Systems (ISCAS), pp. 20–23Google Scholar