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Multimedia Tools and Applications

, Volume 74, Issue 16, pp 6287–6302 | Cite as

NAND flash memory system based on the Harvard buffer architecture for multimedia applications

  • Cheong Ghil Kim
  • Kuinam J. Kim
  • JungHoon LeeEmail author
Article

Abstract

The main purpose of this research is to design a new memory architecture for NAND flash memory to provide XIP (execute in place) for code execution as well as overcome the biggest bottleneck for data execution. NOR flash for multimedia application is particularly well suited for code storage and execute-in-place (XIP) applications, which requires high-speed random access. While NAND flash provides high density and low cost data storage, it is not applicable to XIP applications due to the page access and long access latency. To overcome these limitations, NAND flash can be exploited as code memory for XIP by using SDRAM/SRAM buffer. In order to design the code memory, we proposed a NAND flash with a dual instruction buffer. Furthermore, another enhancement was proposed for the overall system performance by applying a data buffer system to the existing NAND flash memory to reduce the number of write and erase operations; otherwise which could be the biggest bottleneck in a flash memory system. In conclusion, the proposed NAND flash buffer system based on Harvard architecture is operated as main memory as well as the lowest storage device for mobile multimedia system. According to our simulation results, write and erase operations are approximately 60 % and 68 % less than other unified buffer systems, respectively, with two times more space. In addition, the average memory access time is improved by approximately 75 % compared with other unified buffer systems.

Keywords

Flash memory XIP (execute in place) Buffer system Harvard vs von neumann architecture Multimedia applications 

Notes

Acknowledgments

Funding for this paper was provided by Namseoul University.

References

  1. 1.
    Guthaus MR et al. (2001) MiBench: A free, commercially representative embedded benchmark suite. Proc. of the 4th Ann. IEEE Int’l Workshop Workload Characterization, pp. 3–14Google Scholar
  2. 2.
    Hennessy JL, Patterson DA (2006) Computer architecture: a quantitative approach (4/E). Morgan KaufmannGoogle Scholar
  3. 3.
    Huang W, Chen C, Chen C, Chen C (2008) Energy-Efficient buffer architecture of flash memory. Proc. of the Multimedia and Ubiquitous Engineering, pp. 543–546Google Scholar
  4. 4.
    Hyun S, Lee S, Ahn S, Koh K (2008) Improving the demand paging performance with NAND-type Flash Memory. Proc. of the International Conference on Computational Sciences and its Applications, pp. 157–163Google Scholar
  5. 5.
    Igor S (2011) Flash memories. Intech, ISBN 978-953-307-272-2Google Scholar
  6. 6.
    Jo HS, Kang JU, Pack SY (2006) FAB: flash-aware buffer management policy for portable media players. IEEE Trans Consum Electron 52(2):485–493Google Scholar
  7. 7.
    Joo Y, Choi Y, Park C, Chung SW, Chung E, Chang N (2006) Demand paging for OneNAND Flash eXecute-in-place. Proc. of the 4th International Conference on Hardware/Software Codesign and System Synthesis, pp. 229–234Google Scholar
  8. 8.
    Jung B, Lee J (2009) Flash memory system with spatial smart buffer for the substitution of a hard-disk. J of the Korea Soc of Comput and Inform 14(3):41–49Google Scholar
  9. 9.
    Lee J, Park G, Kim S (2005) A new nand-type flash memory package with smart buffer system for spatial and temporal localities. J of Syst Archit 51(2):111–123Google Scholar
  10. 10.
    Mediabench, Available from: <http://euler.slu.edu/~fritts/mediabench>
  11. 11.
    Park C, Seo J, Bae S, Kim H, Kim S, Kim B (2003) A low-cost memory architecture with NAND XIP for mobile embedded systems. Proc of the 1st CODES-ISSS:138–143Google Scholar
  12. 12.
    Park J, Park S, Weems CC, Kim S (2011) A hybrid flash translation layer for SLC-MLC flash memory based multibank solid state disk. Microprocess Microsyst 35(1):48–59Google Scholar
  13. 13.
    Poovey JA (2009) A benchmark characterization of the EEMBC benchmark suite. IEEE Micro 29(5):18–29Google Scholar
  14. 14.
    Przybylski S (1990) The performance impact of block sizes and fetch strategies. Proc. of the 17th Annual International Symposium on Computer Architecture, pp. 160–169Google Scholar
  15. 15.
    Samsung Elec. (2010) NAND flash memory & smart media data bookGoogle Scholar
  16. 17.
    Sanchez FJ, Gonzalez A, Valeo M (1997) Static locality analysis for cache management. Proc. international conference on parallel architectures and compilation techniques, pp. 261– 271Google Scholar
  17. 18.
    Santarini M (2005) NAND versus NOR., available from: < http://www.edn.com/contents/images/6262540.pdf>
  18. 16.
    SimpleScalar LLC, SimpleScalar 3.0, Available from: <http://www.simplescalar.com>
  19. 19.
    Toshiba (2009) NAND vs. NOR flash memory technology overview, available from: < http://umcs.maine.edu/~cmeadow/courses/cos335/Toshiba%20NAND_vs_NOR_Flash_Memory_Technology_Overviewt.pdf>

Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  • Cheong Ghil Kim
    • 1
  • Kuinam J. Kim
    • 2
  • JungHoon Lee
    • 3
    Email author
  1. 1.Department of Computer ScienceNamseoul UniversityCheonanSouth Korea
  2. 2.Department of Convergence SecurityKyonggi UniversitySuwon-siSouth Korea
  3. 3.ERI, Control and Instrument EngineeringGyeongSang National UniversityJinjuSouth Korea

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