Multimedia Tools and Applications

, Volume 61, Issue 1, pp 213–224 | Cite as

Implementation of MAC-based RTL module for Inverse DCT in H.264/AVC



In this paper, we implemented the MAC-based RTL module for inverse DCT in H.264/AVC to improve applicability, to reduce processing time and utilize resources. The paper highlights design of FU architecture, its interconnection topology, regular formula of inverse DCT and array processor mapping as well as MAC-based RTL module constructing. Multi-directional FUA and FPGA were presented along with an evaluated performance and simulation result. Hence, the paper encompasses design of single FU that was verified with the performance test at maximum frequency 200 MHz; the designed 4-by-4 FUA operates over 100 MHz. The proposed multi-directional FU can be extended to n-by-n FUA that functionality can be extended to next video coding standard (H.265/HEVC).


Functional Unit FPGA H.264/AVC Inverse DCT 


  1. 1.
    Hallapuro A, Karczewicz M, Malvar H (2002) “Low Complexity Transform and Quantization-Part 1: Basic Implementation,” JVT doc. JVT-B038, Geneva, FebGoogle Scholar
  2. 2.
    ITU-T (2010) “Joint Collaborative Team on Video Coding,” ITU-T, MayGoogle Scholar
  3. 3.
    ITU-T (2010) “Documents of the first meeting of the JCT-VC—Dresden, Germany,” AprilGoogle Scholar
  4. 4.
    Joint Video Team (JVT) Reference Software. Available :
  5. 5.
    Joint Video Team (JVT) (2002) of ISO/IEC MPEG and ITU-T VCEG, “Advanced Video Coding (ITU-T Rec. H.264, ISO/IEC 14496-19 AVC),” doc JVT-F100, DecGoogle Scholar
  6. 6.
    Joint Video Team (JVT) (2003) of ISO/IEC MPEG and ITU-T VCEG, “Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification (ITU-T Rec. H.264, ISO/IEC 14496019 AVC),” doc JVT-G050, MarGoogle Scholar
  7. 7.
    Kordasiewicz RC, Shirani S (2005) “ASIC and FPGA Implementations of H.264 DCT and Quantization Blocks,” in Proc. IEEE International Conference on Image Processing, pp 1020–1023, SeptGoogle Scholar
  8. 8.
    Lee JS, Jeon YS, Sunwoo MH (2001) “Design of new DSP instructions and their hardware architecture for high-speed FFT,” in Proc. IEEE Workshop on Signal Processing Syst., pp 80–90, SeptGoogle Scholar
  9. 9.
    Richardson IEG (2003) “H.264 and MPEG-4 Video Compression”, WileyGoogle Scholar
  10. 10.
    Richardson IEG (2004) “H.264/MPEG-4 Part 10 White Paper: Transform and Quantization,” MayGoogle Scholar
  11. 11.
    Texas Instruments (2006) “TMS320C64x + DSP Image/Video Processing Library Programmer’s Reference,” Literature number SPRUEB9, MarGoogle Scholar
  12. 12.
    Texas Instruments (2008) “TMS320C64x DSP Two-Level Internal Memory Reference Guide,” Literature number SPRU610C, FebGoogle Scholar
  13. 13.
    Xilinx Co. doc. (2007) “Vertex4 Family Overview,” Sep. Available:

Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  1. 1.Mokwon UniversityDaejeonSouth Korea

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