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Mobile Networks and Applications

, Volume 12, Issue 4, pp 281–291 | Cite as

New and Improved Architectures for Montgomery Modular Multiplication

  • M. Sudhakar
  • R. V. Kamala
  • M. B. Srinivas
Article

Abstract

In this paper an improved Montgomery multiplier, based on modified four-to-two carry-save adders (CSAs) to reduce critical path delay, is presented. Instead of implementing four-to-two CSA using two levels of carry-save logic, authors propose a modified four-to-two CSA using only one level of carry-save logic taking advantage of pre-computed input values. Also, a new bit-sliced, unified and scalable Montgomery multiplier architecture, applicable for both RSA and ECC (Elliptic Curve Cryptography), is proposed. In the existing word-based scalable multiplier architectures, some processing elements (PEs) do not perform useful computation during the last pipeline cycle when the precision is not equal to an exact multiple of the word size, like in ECC. This intrinsic limitation requires a few extra clock cycles to operate on operand lengths which are not powers of 2. The proposed architecture eliminates the need for extra clock cycles by reconfiguring the design at bit-level and hence can operate on any operand length, limited only by memory and control constraints. It requires 2∼15% fewer clock cycles than the existing architectures for key lengths of interest in RSA and 11∼18% for binary fields and 10∼14% for prime fields in case of ECC. An FPGA implementation of the proposed architecture shows that it can perform 1,024-bit modular exponentiation in about 15 ms which is better than that by the existing multiplier architectures.

Keywords

Montgomery modular multiplication RSA ECC carry save adders reconfigurable multiplier scalable multiplier 

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Copyright information

© Springer Science+Business Media, LLC 2007

Authors and Affiliations

  1. 1.Center for VLSI and Embedded System TechnologiesInternational Institute of Information TechnologyHyderabadIndia

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