Higher-Order and Symbolic Computation

, Volume 24, Issue 1–2, pp 81–114 | Cite as

Static consistency checking for Verilog wire interconnects

Using dependent types to check the sanity of Verilog descriptions
  • Cherif Salama
  • Gregory Malecha
  • Walid Taha
  • Jim Grundy
  • John O’Leary


The Verilog hardware description language has padding semantics that allow designers to write descriptions where wires of different bit widths can be interconnected. However, many such connections are nothing more than bugs inadvertently introduced by the designer and often result in circuits that behave incorrectly or use more resources than required. A similar problem occurs when wires are incorrectly indexed by values (or ranges) that exceed their bounds. These two problems are exacerbated by generate blocks. While desirable for reusability and conciseness, the use of generate blocks to describe circuit families only makes the situation worse as it hides such inconsistencies. Inconsistencies in the generated code are only exposed after elaboration when the code is fully-expanded.

In this paper we show that these inconsistencies can be pinned down prior to elaboration using static analysis. We combine dependent types and constraint generation to reduce the problem of detecting the aforementioned inconsistencies to a satisfiability problem. Once reduced, the problem can easily be solved with a standard satisfiability modulo theories (SMT) solver. In addition, this technique allows us to detect unreachable code when it resides in a block guarded by an unsatisfiable set of constraints. To illustrate these ideas, we develop a type system for Featherweight Verilog (FV), a core calculus of structural Verilog with generative constructs and previously defined elaboration semantics. We prove that a well-typed FV description will always elaborate into an inconsistency-free description. We also provide an open-source implementation demonstrating our approach.


Verilog elaboration Static array bounds checking Verilog wire width consistency Dead code elimination Dependent types 


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Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  • Cherif Salama
    • 1
  • Gregory Malecha
    • 1
  • Walid Taha
    • 1
  • Jim Grundy
    • 2
  • John O’Leary
    • 2
  1. 1.Rice UniversityHoustonUS
  2. 2.Intel Strategic CAD LabsHillsboroUSA

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