Failure analysis of EOS-induced damage at final electrical testing
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The performance and productivity of microelectronics has increased continuously over more than four decades due to enormous advances in photolithography, wafer size, process technology, and devices. Historically, electrical overstress (EOS) has been one of the leading causes of integrated circuit failures. In this paper, the failure sites are observed on an antiparallel diode string within a power cut cell of a 130 nm complementary metal oxide semiconductor mix-signal chip during testing. It was found that the diode string was driven with a forward biased pulse during the power-up and power-down conditions. The slow rise time of the energy pulse indicates that the electrical failure is associated with an EOS event. Failures are verified using scanning electronic microscopy, photoemission microscopy, and liquid crystal analysis. The cause of the failure is either the supply voltage or a timing error in the final testing of the devices.
KeywordsComplementary Metal Oxide Semiconductor Very Large Scale Integration Automatic Test Equipment Integrate Circuit Electrical Failure
The authors wish to acknowledge the assistance and support of National Science Council, R.O.C., under Grant NSC 101-2221-E-214-077.
- 2.G. Gielen, E. Maricau, P. De Wit, Analog circuit reliability in sub-32 nanometer CMOS: analysis and mitigation. in Design, Automation Test in Europe Conf. Exhibition (DATE), 2011 (2011), pp. 1–6Google Scholar
- 5.G. Wagner, J.M. Soden, C.F. Hawkins, Extent and cost of EOS/ESD amages in an IC manufacturing process. in Proceedings of the EOS/ESD Symposium (1993), pp. 49–55Google Scholar
- 6.Intel. ESD/EOS Intel Manufacturing Guide, (2010), http://www.intel.com/content/dam/www/public/us/en/documents/guides/ch3-esd-eos-guide.pdf
- 7.H.W. Tsai, M.D. Ker, Layout consideration and circuit solution to prevent EOS failure induced by Latchup test in a high-voltage integrated circuits. IEEE Trans. Device Mater. Rel. 11(3), 1–7 (2012)Google Scholar
- 8.H.S. Lin, C.M. Chen, K.H. Chen, A. Wang, A case study of defects due to process marginalities in deep sub-micron technology. in 18th ESREF Proceedings (2007), pp. 1604–1608Google Scholar
- 9.A.K. Yahya, N.T. Yusof, Y.M. Yusof, Noble failure analysis procedure for Trench MOSFET technology devices through detail electrical parameter characterization and unique fault isolation technique. in 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) (2012), pp. 1–6Google Scholar
- 10.H. Lin, M. Khan, T. Giao, Dynamic liquid crystal hot spot examination of functional failures on production testers. in Proceedings from the 20th International Symposium for Testing and Failure Analysis (1994), p. 81Google Scholar
- 11.M.D. Ker, C.Y. Wu, H.H. Chang, T.S. Wu, Whole-chip ESD protection scheme for CMOS mixed-mode IC’s in deep-submicron CMOS technology. in Proceeding of IEEE Custom Integrated Circuits Conference (1997), pp. 31–34Google Scholar
- 13.T. Maloney, S. Dabral, Novel clamp circuits for IC power supply protection. in Proceeding EOS/ESD Symposium (1995), pp. 1–12Google Scholar
- 16.M.K. Chen, Y.J. Huang, S.L. Fu, Experimental approach to analyze failure site condition in final testing of BGA package. in 13th Annual Pan Pacific Microelectronics Symposium (Kauai, Hawaii, USA, 2008)Google Scholar
- 17.J. Colvin, Functional failure analysis by induced stimulus. in Proceedings of International Symposium for Testing and Failure Analysis (2002), pp. 623–630Google Scholar