Skip to main content
Log in

Formation and simulation of a thermally stable NiSi FUSI gate electrode by a novel integration process

  • Published:
Journal of Materials Science: Materials in Electronics Aims and scope Submit manuscript

Abstract

The low resistivity nickel fully silicided (FUSI) gate have received increasing attention over the past several years due to the simply integration scheme for implementation and ease of passivation of the underlying gate dielectric for sub-65 nm/45 nm CMOS devices. A mixed-phase of nickel silicide layer was commonly observed during phase transformation. In order to obtain a thermally stable Ni-FUSI gate electrode, we developed a unique integration process to achieve NiSi phase stabilize at temperature 900 °C and delay the agglomeration of NiSi. For the first time, we established an effective way to identify the phase transformations by some nondestructive techniques such as X-ray diffraction, sheet resistance measurement and AFM analysis. The correlations between its electrical and morphological changes during Ni-Si phase transformation were presented. F-incorporation demonstrated some improvements in both morphology and phase stability of the NiSi films at high processing temperatures. Furthermore, modeling the effect of dopants in NiSi on nano-sizes MOSFETs devices was implemented by ISE-TCAD. A low threshold voltage can be tuned by pre-doping the poly-Si with Sb for sub-45 nm NFET devices.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11

Similar content being viewed by others

Reference

  1. H. Iwai, T. Ohgura, S. Ohmi, Microelectron. Eng. 60, 157 (2002)

    Article  CAS  Google Scholar 

  2. A. Hokazono, K. Ohuchi, M. Takayanagi, Y. Watanabe, S. Magoshi, Y. Kato, T. Shimizu et al., IEDM Tech. Dig. 639 (2002)

  3. J.P. Lu, D. Miles, J. Zhao, A. Gurba, Y. Xu, C. Lin, M. Hewson et al., IEDM Tech. Dig. 371 (2002)

  4. Z. Ma, L.H. Allen, Phys. Rev. B 49, 13501 (1994)

    Google Scholar 

  5. K. Maex, Mater. Sci. Eng. R 11, 53 (1993)

    Google Scholar 

  6. R.N. Huang, J.Y. Feng, Y. Huang, Appl. Surf. Sci. 207, 139 (2003)

    Article  CAS  Google Scholar 

  7. X.P. Qu, C. Detavernier, R.L. Van Meirhaeghe, F. Cardon, MRS Proc. 670, K6101–K6106 (2001)

    Google Scholar 

  8. C. Detavernier, X.P. Qu, L. Van Meirhaeghe, J. Mater. Res. 18, 1675 (2003)

    Article  Google Scholar 

  9. A. Lauwers, A. Steegen, M. de Potter, R. Lindsay, A. Satta, H. Bender, K. Maex, J. Vac. Sci. Technol. B 19, 2026 (2001)

    Google Scholar 

  10. A. Lauwers, M. de Potter, O. Chamirian, R. Lindsay, C. Demeurisse, C. Vrancken, K. Maex, Microelectron. Eng. 64, 131 (2002)

    Article  CAS  Google Scholar 

  11. K.L Pey, P.S. Lee, D. Mangelinck, Thin Solid Films 462–463, 137 (2004)

    Article  CAS  Google Scholar 

  12. M. Qin, V.M.C. Poon, S.C.H. Ho, J. Electrochem. Soc. 148, 271 (2001)

    Article  Google Scholar 

  13. W.P. Maszara, Z. Krivokapic, P. King, J.-S. Goo, M.-R. Lin, 2002 IEDM Tech. Dig. 367, (2002)

  14. M.A. Pawlak, A. Lauwers, T. Janssens, K.G. Anil, K. Opsomer, K. Maex, A. Vantomme, J.A. Kittl, IEEE Electron Device Lett. 27, 99 (2006)

    Google Scholar 

  15. ISE Systems, TCAD Suite, http://www.ise.com

  16. Integrated System Engineering, ISE TCAD, AG, Zurich, Switzerland, 1998

  17. F. Heurle, C.S. Petersson, J.E.E. Baglin, S.J. Placa, C.Y. Wong, J. Appl. Phys. 55, 4208 (1984)

    Article  Google Scholar 

  18. J.A. Kittl, A. Lauwers, O. Chamirian, M.A. Pawlak, M. Van Dal, A. Akheyar, M. De Potter, A. Kottantharayil, G. Pourtois, R. Lindsay, K. Maex, Mater. Res. Soc., Symp. Proc. 810, 31 (2004)

    CAS  Google Scholar 

  19. C. Lavoie, F.M. d’Heurle, C. Detavernier, C. Cabral Jr., Microelectron. Eng. 70, 144 (2003)

    Article  CAS  Google Scholar 

  20. J.A. Kittl, A. Lauwers, M.A. Pawlak, M. Van Dal, A. Veloso, K.G. Anil, G. Pourtois, C. Demeurisse, T. Schram, B. Brijs, M. De Potter, C. Vrancken, K. Maex, Microelectron. Eng. 82, 441 (2005)

    Article  CAS  Google Scholar 

  21. A.S. Wang, D.Z. Chi, M. Loomans, D. Ma, M.Y. Lai, W.C. Tjiu, S.J. Chua, Appl. Phys. Lett. 81, 5138 (2002)

    Article  CAS  Google Scholar 

Download references

Acknowledgments

The authors would like to thank W.F. Wu for technical assistance and Chiung-Chih Hsu for TEM analysis at National Nano Device Laboratories. This work was supported by the National Science Council under award no. NSC94-2218-E-034-004.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to S. Y. Tan.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Tan, S.Y., Chiu, HC., Chen, YY. et al. Formation and simulation of a thermally stable NiSi FUSI gate electrode by a novel integration process. J Mater Sci: Mater Electron 19, 411–417 (2008). https://doi.org/10.1007/s10854-007-9355-9

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10854-007-9355-9

Keywords

Navigation