A thermally robust Ni-FUSI process using in 65 nm CMOS technology
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The interest in the low resistivity fully silicided (FUSI) gate increased significantly because of promising in use as contact to the source, drain, and gate for sub−65 nm/45 nm CMOS devices. NiSi is potentially an attractive material due to its capability to maintain low resistivity even for channel length down to 100 nm. The Formation of thermally stable silicide gates is important for improving the devices fabrication processes. In order to obtain a thermally stable Ni-FUSI gate electrode, we introduced a two-step annealing process associated with properly tuned thickness of the initial Ni film and additional of implantation of BF2 during the poly-gate formation to push the transformation of NiSi2 to higher temperatures at about 900°C and retard agglomeration. A mixed-phase of nickel silicide layer was commonly observed during phase transformation. For the first time, we established an effective way to identify the phase transformations by some nondestructive techniques such as X-ray diffraction, sheet resistance measurement and AFM analysis. The correlations between its electrical and morphological changes during Ni–Si phase transformation were presented. Furthermore, the effect with addition amount of BF2 impurities into NiSi was investigated. F-incorporation demonstrated some improvements in both morphology and phase stability of the NiSi films at high processing temperatures.
KeywordsSheet Resistance Nickel Silicide Equivalent Oxide Thickness Sheet Resistance Measurement NiSi Phase
The authors would like to thank Ming-Hsin Cheng for technical assistance and XRD analysis at National Nano Device Laboratories. This work was supported by the National Science Council under award no. NSC94-2218-E-034-004.
- 1.The International Technology Roadmap for Semiconductors, 2005Google Scholar
- 2.C. Hobbs et al., VLSI Symp. Tech. Dig. (2003), p. 9Google Scholar
- 3.K. Shiraishi et al., VLSI Symp. Tech. Dig. (2004), p. 108Google Scholar
- 5.A. Hokazono, K. Ohuchi, M. Takayanagi, Y. Watanabe, S. Magoshi, Y. Kato, T. Shimizu et al., IEDM Tech. Dig. (2002), p. 639Google Scholar
- 6.J.P. Lu, D. Miles, J. Zhao, A. Gurba, Y. Xu, C. Lin, M. Hewson et al., IEDM Tech. Dig. (2002), p. 371Google Scholar
- 10.X.P. Qu, C. Detavernier, R.L. Van Meirhaeghe, F. Cardon, MRS Proc. 670, K6101–K6106 (2001)Google Scholar
- 11.C. Detavernier, X.P. Qu, L. Van Meirhaeghe, J. Mater. Res. 18, 1675 (2003)Google Scholar
- 18.J.A. Kittl, A. Lauwers, O. Chamirian, M.A. Pawlak, M. Van Dal, A. Akheyar, M. De Potter, A. Kottantharayil, G. Pourtois, R. Lindsay, K. Maex, Mater. Res. Soc., Symp. Proc. 810, 31 (2004)Google Scholar