Skip to main content

Advertisement

Log in

Manufacturing intelligence to forecast and reduce semiconductor cycle time

  • Published:
Journal of Intelligent Manufacturing Aims and scope Submit manuscript

Abstract

Semiconductor manufacturing is one of the most complicated production processes with the challenges of dynamic job arrival, job re-circulation, shifting bottlenecks, and lengthy fabrication process. Owing to the lengthy wafer fabrication process, work in process (WIP) usually affects the cycle time and throughput in the semiconductor fabrication. As the applications of semiconductor have reached the era of consumer electronics, time to market has played an increasingly critical role in maintaining a competitive advantage for a semiconductor company. Many past studies have explored how to reduce the time of scheduling and dispatching in the production cycle. Focusing on real settings, this study aims to develop a manufacturing intelligence approach by integrating Gauss-Newton regression method and back-propagation neural network as basic model to forecast the cycle time of the production line, where WIP, capacity, utilization, average layers, and throughput are rendered as input factors for indentifying effective rules to control the levels of the corresponding factors as well as reduce the cycle time. Additionally, it develops an adaptive model for rapid response to change of production line status. To evaluate the validity of this approach, we conducted an empirical study on the demand change and production dynamics in a semiconductor foundry in Hsinchu Science Park. The approach proved to be successful in improving forecast accuracy and realigning the desired levels of throughput in production lines to reduce the cycle time.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

References

  • Atherton R. W., Dayhoff J. E. (1986) Signature analysis: Simulation of inventory, cycle time, and throughput trade-offs in wafer fabrication. IEEE Transactions on Components, Hybrids, and Manufacturing Technology 9(4): 498–507

    Article  Google Scholar 

  • Chen H., Harrison J. M., Mandelbaum A., van Ackere A., Wein L. M. (1988) Empirical evaluation of a queueing network model for semiconductor wafer fabrication. Operations Research 36(2): 202–215

    Article  Google Scholar 

  • Chien C.-F., Chen C. (2007) Using genetic algorithms (GA) and a coloured timed Petri net (CTPN) for modelling the optimization-based schedule generator of a generic production scheduling system. International Journal of Production Research 45(8): 1763–1789

    Article  Google Scholar 

  • Chien C.-F., Chen Y., Peng J. (2010) Manufacturing intelligence for semiconductor demand forecast based on technology diffusion and product life cycle. International Journal of Production Economics 128(2): 496–509

    Article  Google Scholar 

  • Chien C.-F., Hsiao A., Wang I. (2004) Constructing semiconductor manufacturing performance index and applying data mining for manufacturing data analysis. Journal of Chinese Institute of Industrial Engineering 21(4): 313–327

    Article  Google Scholar 

  • Dabbas R. M., Chen H. N. (2001) Mining semiconductor manufacturing data for productivity improvement—an integrated relational database approach. Computers in Industry 45(1): 29–44

    Article  Google Scholar 

  • Fowler, J. W., Brown, S., Gold, H., & Schoemig, A. (1997). Measure improvement in cycle-time-constrained capacity. In Proceedings of the 6th IEEE international symposium on semiconductor manufacturing (pp. 21–24).

  • Fowler J. W., Park S., Mackulak G. T., Shunk D. L. (2001) Efficient cycle time-throughput curve generation using a fixed sample size procedure. International Journal of Production Research 39(12): 2595–2613

    Article  Google Scholar 

  • Kumar K., Alsaleh M. A. (1996) A comparative study for the estimation of parameters in nonlinear models. Applied Mathematics and Computation 77(2–3): 179–183

    Article  Google Scholar 

  • Kuo C., Chien C., Chen C. (2011) Manufacturing intelligence to exploit the value of production and tool data to reduce cycle time. IEEE Transactions on Automation Science and Engineering 8(1): 103–111

    Article  Google Scholar 

  • Leachman R. C., Kang J., Lin V. (2002) SLIM: Short cycle time and low inventory in manufacturing at samsung electronics. Interfaces 32(1): 61–77

    Article  Google Scholar 

  • Miltenburg J., Sparling D. (1996) Managing and reducing total cycle time: Models and analysis. International Journal of Production Economics 46–47: 89–108

    Article  Google Scholar 

  • Moore G. E. (1965) Cramming more components onto integrated circuits. Electronics 38(8): 114–117

    Google Scholar 

  • Morrison J. R., Martin D. P. (2007) Practical extensions to cycle time approximations for the G/G/m-Queue with applications. IEEE Automation Science and Engineering 4(4): 523–532

    Article  Google Scholar 

  • Papadopoulos H. T., Vidalis M. I. (2001) Minimizing WIP inventory in reliable production lines. International Journal of Production Economics 70(2): 185–197

    Article  Google Scholar 

  • Sattler, L. (1996). Using queuing curve approximation in a fab to determine productivity improvement. In Proceedings of 1996 advanced semiconductor manufacturing conference and workshop (pp. 140–145).

  • Seber G. A. F., Wild C. J. (1989) Nonlinear regression. Wiley, New York

    Book  Google Scholar 

  • Yu C., Huang H. (2002) On-line learning delivery decision support system for highly product mixed semiconductor foundry. IEEE Transactions on Semiconductor Manufacturing 15(2): 274–278

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Chia-Yu Hsu.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Chien, CF., Hsu, CY. & Hsiao, CW. Manufacturing intelligence to forecast and reduce semiconductor cycle time. J Intell Manuf 23, 2281–2294 (2012). https://doi.org/10.1007/s10845-011-0572-y

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10845-011-0572-y

Keywords

Navigation