Abstract
Growing demand for high speed processing of streamed data (e.g. video-streams, digital signal streams, communication streams, etc.) in the advanced manufacturing environments requires the adequate cost-efficient stream-processing platforms. Platforms based on the embedded microprocessors often cannot satisfy performance requirements due to limitations associated with the sequential nature of data execution process. During the last decade, development and prototyping of the above embedded platforms has started moving towards utilization of the Field Programmable Gate Array (FPGA) devices. However, the programming of an application to the FPGA based platform became an issue due to relatively complicated hardware design process. The paper presents an approach which allows simplification of the application programming process by utilization of: (i) the uniformed FPGA platform with the dynamically reconfigurable architecture, (ii) a programming technique based on a temporal partitioning of the application in segments which can be described in terms of macro-operators (function specific virtual components). The paper describes the concept of the approach, presents the analytical investigation and experimental verification of the cost-effectiveness of the proposed platform comparing to the platforms based on sequential micro-processors. It is also shown that the approach can be beneficially utilized in collaborative design and manufacturing.
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Alsolaim, A., Starzyk, J., Becker, J., & Glesner, M. (2000). Architecture and application of a dynamically reconfigurable hardware array for future mobile communication systems. In 2000 IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM, p. 205.
AMIRIX AP1000 Virtex-II PCI Platform FPGA Development Board. http://www.nuhorizons.com/services/development/amirix/ .
Dasu A., Panchanathan S. (2002) Reconfigurable media processing. Parallel Computing 28(7–8): 1111–1139
De Micheli, G. (1994). Synthesis and optimization of digital circuits (Chapter 4, 579 pp). McGraw-Hill.
FIPA: The Foundation for Intelligent Physical Agents. http://www.fipa.org, 2007.
Goldblatt, K. (2001). Xilinx application note XAPP178 “Parallel configuration protocol”. Xilinx Press.
Goldstein S.C., Schmit H., Budiu M., Cadambi S., Moe M., Taylor R.R. (2000) PipeRench: A reconfigurable architecture and compiler. Computer 33(4): 70–77
Hartenstein, R. (2001). A decade of reconfigurable computing: A visionary retrospective. Design, Automation and Test in Europe, 2001. Conference and Exhibition 2001, Proceedings, pp. 642–649.
Hennessy, J., & Patterson, D. (2003) Computer architecture. A quantitative approach (3rd ed., Chapter 1, 884 pp). Morgan Kaufmann Publishers.
JADE: Java Agent Development Framework. http://sharon.cselt.it/projects/jade, 2004.
Kaul, M., Vemuri, R., Govindarajan, S., & Ouaiss, I. (1998). An automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of DSP applications. Design Automation Conference, 1999. Proceedings 36th, pp. 616–622.
Kessal L., Abel N., Demigny D. (2003) Real-time image processing with dynamically reconfigurable architecture. Real-Time Imaging 9(5): 297–313
Kirischian, V., Zhelnakov, S. Chun, P. W., Kirischian, L., & Geurkov, V. (2005). Uniform reconfigurable processing module for design and manufacturing integration. Advanced Manufacturing Technologies Conference Proceedings, pp. 77–82.
Maturana F., Shen W., Norrie D. (1999) MetaMorph: An adaptive agent-based architecture for intelligent manufacturing. International Journal of Production Research 37(10): 2159–2174
Mesquita, D., Moraes, F., Palma, J., Moller, L., & Calazans, N. (2003). Remote and partial reconfiguration of FPGAs: Tools and trends. Parallel and Distributed Processing Symposium, 2003. Proceedings International, 22–26 April 2003, p. 8.
Oldknow K.D., Yellowley I. (2001) Design, implementation and validation of a system for the dynamic reconfiguration of open architecture machine tool controls. International Journal of Machine Tools and Manufacture 41(6): 795–808
Oldknow K.D., Yellowley I. (2003) Implementation and validation of 3-dimensional dynamic interpolation using an FPGA based controller. International Journal of Machine Tools & Manufacture 43(9): 937–45
Oldknow K.D., Yellowley I. (2005) FPGA-based servo control and three-dimensional dynamic interpolation. IEEE/ASME Transactions on Mechatronics 10(1): 98–110
Tanougast C., Berviller Y., Brunet P., Weber S., Rabah H. (2003) Temporal partitioning methodology optimizing FPGA resources for dynamically reconfigurable embedded real-time system. Microprocessors and Microsystems 27(3): 115–130
Xilinx Virtex II Platform FPGA. (2000). Handbook VG002.
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Kirischian, V., Geurkov, V., Chun, P.W. et al. Macro-programmable reconfigurable stream processor for collaborative manufacturing systems. J Intell Manuf 19, 723–734 (2008). https://doi.org/10.1007/s10845-008-0123-3
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DOI: https://doi.org/10.1007/s10845-008-0123-3