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Pre-Silicon Verification Using Multi-FPGA Platforms: A Review

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Abstract

Because of the shrinking transistor size and improved design process, the computation capability of modern digital systems has increased tremendously over the past few years. This, however, has led to increased design complexity and huge verification efforts and costs. The design of new digital systems costs millions of dollars and the money is wasted if the final product does not serve the purpose. This has made pre-silicon verification even more pertinent as it can detect design faults prior to its roll out and can save companies a huge fortune. Pre-silicon verification now accounts for almost 70% of the total design effort and cost of modern digital systems. For pre-silicon verification, four techniques are commonly used namely simulation, emulation, virtual prototyping and FPGA-based prototyping. These techniques have their advantages and disadvantages. However, FPGA-based prototyping is unique in the sense it gives better speed and real world testing experience as compared to other pre-silicon verification techniques. In this paper, we give a detailed survey of multi-FPGA prototyping. A survey of three different multi-FPGA platforms namely off-the-shelf, custom, and cabling platform is presented in this work. A comprehensive overview of these platforms from hardware perspective is presented. Detailed discussion on their respective back end flow and the associated difference is also presented. The survey is concluded with a discussion on the challenges faced by multi-FPGA prototyping and the research opportunities where work can be done for further improvement.

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Authors and Affiliations

  1. Electrical and Computer Engineering Department, Dhofar University, Salalah, Oman

    Umer Farooq

  2. SoC, LiP6, Sorbonne Universite, Paris, France

    Habib Mehrez

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  1. Umer Farooq
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  2. Habib Mehrez
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Correspondence to Umer Farooq.

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Farooq, U., Mehrez, H. Pre-Silicon Verification Using Multi-FPGA Platforms: A Review. J Electron Test 37, 7–24 (2021). https://doi.org/10.1007/s10836-021-05929-1

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