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A Layout-Based Rad-Hard DICE Flip-Flop Design

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Abstract

The DICE flip-flop has been rendered ineffective in deep-submicron technology nodes (e.g. 65 nm and 28 nm) due to charge sharing when exposed to single event strikes. This paper presents a new single event upset tolerant flip-flop design by applying the hardening technique on DICE at the layout level. This approach is an alternative to existing Layout Design through Error-Aware Transistor Positioning (LEAP); it also re-places transistors in master and slave DICE latches in the zigzag fashion in the layout. Both computer simulations and heavy-ion experimental results demonstrate that our proposed layout design has no single event upset errors under normal strikes until LET = 37 MeV·cm2/mg compared to the traditional DICE structure.

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References

  1. Amusan OA, Witulski AF, Massengill LW, Bhuva BL, Fleming PR, Alles ML, Sternberg AL, Black JD, Schrimpf RD (2006) Charge collection and charge sharing in a 130 nm CMOS technology. IEEE Trans Nucl Sci 53(6):3253–3258

    Article  Google Scholar 

  2. Baumann R (2005) Soft errors in advanced computer systems. IEEE Des Test Comput 22(3):258–266

    Article  Google Scholar 

  3. Baze MP, Hughlock B, Wert J, Tostenrude J, Massengill L, Amusan O, Lacoe R, Lilja K, Johnson M (2008) Angular dependence of single event sensitivity in hardened flip/flop designs. IEEE Trans Nucl Sci 55(6):3295–3301

    Article  Google Scholar 

  4. Black JD, Sternberg AL, Alles ML, Witulski AF, Bhuva BL, Massengill LW, Benedetto JM, Baze MP, Wert JL, Hubert MG (2005) HBD layout isolation techniques for multiple node charge collection mitigation. IEEE Trans Nucl Sci 52(6):2536–2541

    Article  Google Scholar 

  5. Cabanas-Holmen M, Cannon EH, Rabaa S, Amort T, Ballast J, Carson M, Lam D, Brees R (2013) Robust SEU mitigation of 32 nm dual redundant Flip-flops through interleaving and sensitive node-pair spacing. IEEE Trans Nucl Sci 60(6):4374–4380

    Article  Google Scholar 

  6. Calin T, Nicolaidis M, Velazco R (1996) Upset hardened memory design for submicron CMOS technology. IEEE Trans Nucl Sci 43(6):2874–2878

    Article  Google Scholar 

  7. Dodd PE, Massengill LW (2003) Basic mechanism and modeling of single-event upset in digital microelectronics. IEEE Trans Nucl Sci 50(3):583–602

    Article  Google Scholar 

  8. Eftaxiopoulos N, Axelos N, Zervakis G et al (2015) Delta DICE: A Double Node Upset resilient latch. In: Proc IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS), Fort Collins, pp 1–4

  9. Gaspard NJ, Jagannathan S, Diggins ZJ, King MP, Wen SJ, Wong R, Loveless TD, Lilja K, Bounasser M, Reece T, Witulski AF, Holman WT, Bhuva BL, Massengill LW (2013) Technology scaling comparison of flip-flop heavy-ion single-event upset cross sections. IEEE Trans Nucl Sci 60(6):4368–4373

    Article  Google Scholar 

  10. Haghi M, Draper J (2009) The 90 nm double-DICE storage element to reduce single-event upsets. In: Proc. 52nd IEEE International Midwest Symposium on Circuits and Systems, Cancun, pp 463–466

    Google Scholar 

  11. Hoff JR (2006) Redundant single event suppression system. US Patent 7023235B2, 2006-4-4

  12. Hsiao-Heng Kelin L, Klas L, Mounaim B et al (2010) LEAP: layout design through error-aware transistor positioning for soft-error resilient sequential cell design. In: Proc. IEEE Reliability Physics Symposium, pp 203–212

    Google Scholar 

  13. TFIT (2014) IROC Technologies. https://www.iroctech.com/solutions/transistorcell-level-fault-simulationtools-and-services/tfit-qa/. Accessed 1 Aug 2018

  14. Jiang J, Xu Y, Ren J, Zhu W, Lin D, Xiao J, Kong W, Zou S (2018) Low-cost single event double-upset tolerant latch design. Electron Lett 54(9):554–556

    Article  Google Scholar 

  15. Katsarou K, Tsiatouhas Y (2014) Double node charge sharing SEU tolerant latch design. In: Proc IEEE 20th International On-Line Testing Symposium (IOLTS), Platjad'Aro, Girona, pp 122–127

    Google Scholar 

  16. Lee HK, Lilja K, Bounasser M et al (2011) Design framework for soft-error-resilient sequential cells. IEEE Trans Nucl Sci 58(6):3026–3032

    Article  Google Scholar 

  17. Li Y-Q, Wang H–B, Liu R et al (2016) A 65 nm temporally hardened Flip-flop circuit. IEEE Trans Nucl Sci 63(6):2934–2940

    Article  Google Scholar 

  18. Li Y-Q, Wang H-B, Liu R et al (2017) A Quatro-based 65-nm Flip-flop circuit for soft-error resilience. IEEE Trans Nucl Sci 64(6):1554–1561

    Article  Google Scholar 

  19. Maru A, Shindou H, Ebihara T et al (2010) DICE-based Flip-flop with SET pulse discriminator on a 90 nm bulk CMOS process. IEEE Trans Nucl Sci 57(6):3602–3608

    Google Scholar 

  20. Narasimham B, Gambles JW, Shuler RL et al (2009) Quantifying the effect of guard rings and guard drains in mitigating charge collection and charge spread. IEEE Trans Nucl Sci 55(6):3456–3460

    Article  Google Scholar 

  21. Naseer R, Draper J (2006) DF-DICE: a scalable solution for soft error tolerant circuit design. In: Proc. 2006 IEEE International Symposium on Circuits and Systems, Island of Kos, pp 3890–3893

    Google Scholar 

  22. Normand E (1996) Single event upset at ground level. IEEE Trans Nucl Sci 43(6):2742–2750

    Article  Google Scholar 

  23. Olson BD, Ball DR, Warren KM et al (2006) Simultaneous single event charge sharing and parasitic bipolar conduction in a highly-scaled SRAM design. IEEE Trans Nucl Sci 52(6):2132–2136

    Article  Google Scholar 

  24. Olson BD, Amusan OA, Dasgupta S, Massengill LW, Witulski AF, Bhuva BL, Alles ML, Warren KM, Ball DR (2007) Analysis of parasitic PNP bipolar transistor mitigation using well contacts in 130 nm and 90 nm CMOS technology. IEEE Trans Nucl Sci 54(4):894–897

    Article  Google Scholar 

  25. Restle PJ, McNamara TG, Webber DA, Camporese PJ, Eng KF, Jenkins KA, Allen DH, Rohn MJ, Quaranta MP, Boerstler DW, Alpert CJ, Carter CA, Bailey RN, Petrovick JG, Krauter BL, McCredie BD (2001) A clock distribution network for microprocessors. IEEE J Solid State Circuits 36(5):792–799

    Article  Google Scholar 

  26. Wang H–B, Li Y-Q, Chen L et al (2015) An SEU-tolerant DICE latch design with feedback transistors. IEEE Trans Nucl Sci 62(2):548–554

    Article  Google Scholar 

  27. Zhao Y, Wang L, Yue S, Wang D, Zhao X, Sun Y, Li D, Wang F, Yang X, Zheng H, Ma J, Fan L (2015) SEU and SET of 65 bulk CMOS Flip-flops and Their implications for RHBD. IEEE Trans Nucl Sci 62(6):2666–2672

    Article  Google Scholar 

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Acknowledgments

This work is supported by the Fundamental Research Funds for the Central Universities (2016B07414 & 2018B49614) and by the opening fund of Key Laboratory of Silicon Device Technology, Chinese Academy of Sciences. It is also supported through Innovation Foundation of Radiation Application, China Institute of Atomic Energy under contract No. KFZC2018040205.

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Authors and Affiliations

  1. College of IoT Engineering, Hohai University, Changzhou, 213022, China

    Haibin Wang, Xixi Dai, Younis Mohammed Younis Ibrahim & Hongwen Sun

  2. College of Engineering, University of Saskatchewan, Saskatoon, S7N 5A9, Canada

    Haibin Wang & Li Chen

  3. Innovation Foundation of Radiation Application, China Institute of Atomic Energy, Beijing, 102413, China

    Haibin Wang, Li Cai & Gang Guo

  4. iRoC Technologies, 38000, Grenoble, France

    Issam Nofal

  5. Beijing Institute of Spacecraft Environment Engineering, Beijing, 100094, China

    Zicai Shen

Authors
  1. Haibin Wang
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  2. Xixi Dai
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  3. Younis Mohammed Younis Ibrahim
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  4. Hongwen Sun
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  5. Issam Nofal
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  6. Li Cai
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  7. Gang Guo
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  8. Zicai Shen
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  9. Li Chen
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Correspondence to Haibin Wang.

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Responsible Editor: V. D. Agrawal

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Wang, H., Dai, X., Ibrahim, Y.M.Y. et al. A Layout-Based Rad-Hard DICE Flip-Flop Design. J Electron Test 35, 111–117 (2019). https://doi.org/10.1007/s10836-019-05773-4

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  • DOI: https://doi.org/10.1007/s10836-019-05773-4

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