Skip to main content
SpringerLink
Log in

Path Representation in Circuit Netlists Using Linear-Sized ZDDs with Optimal Variable Ordering

  • Published:
Journal of Electronic Testing Aims and scope Submit manuscript

Abstract

The efficient representation and manipulation of a large number of paths in a Directed Acyclic Graph (DAG) requires the usage of special data structures that may become of exponential size with respect to the size of the graph. Several methodologies targeting Electronic Design Automation problems such as timing analysis, physical design, verification and testing involve path representation and necessary manipulation. Previous works proposed an encoding using Zero-suppressed Binary Decision Diagrams (ZDDs), which has been shown experimentally to cope well when representing structural or logical paths in VLSI circuits. However, it is well known that the ordering of the variables in a ZDD highly affects its size and, therefore, the efficiency of the methodologies utilizing these data structures. In this work, we show that using a reverse topological order for the ZDD variables bounds the number of nodes in the ZDD representing structural paths to the number of edges in the DAG considered, hence, making the ZDD size linear to the DAG’s size. This result, supported here both theoretically and experimentally, is very important as it can render methodologies with questionable scalability applicable to larger industrial designs. We demonstrate the applicability of the proposed variable ordering in one such methodology which utilizes ZDDs to grade the Path Delay Fault coverage of a given test set.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7

Similar content being viewed by others

Notes

  1. This definition of the variable order is in accordance with the one proposed in [6] where Ordered BDDs were introduced, and is the one mostly used in the related literature. The work of [31] uses a definition for the variable order in the completely opposite fashion, i.e., nodes with higher order appear above nodes with lower order. While this does not affect the nature of the proposed work, we have changed the procedures of Fig. 4 to follow the most common definition, as in [6].

  2. We have chosen to compare with [25] instead of the same authors’ previous work in [24] which proposes a specific variable ordering, as the results in [25] demonstrate small improvement over [24].

References

  1. Ababei C, Selvakkumaran N, Bazargan K, Karypis G (2002) Multi-objective circuit partitioning for cutsize and path-based delay minimization. In: Proceedings of international conference on CAD, pp 181–185

  2. Abdulrazzaq NM, Gupta SK (2003) Path-delay fault simulation for circuits with large numbers of paths for very large test sets. In: Proceedings of VLSI test symposium, pp 186–193

  3. Abramovici M, Menon P, Miller DT (1984) Critical path tracing: an alternative to fault simulation. IEEE Des Test Comput 1(1):83–93

    Article  Google Scholar 

  4. Aloul FA, Markov IL, Sakallah KA (2004) Mince: a static global variable-ordering heuristic for SAT search and BDD manipulation. J UCS 10(12):1562–1596

    Google Scholar 

  5. Bollig B, Wegener I (1996) Improving the variable ordering of OBDDs is NP-complete. IEEE Trans Comput 45(9):993–1002

    Article  Google Scholar 

  6. Bryant R (1986) Graph-based algorithms for boolean function manipulation. IEEE Trans Comput C-35 (8):677–691

    Article  Google Scholar 

  7. Cheng KT, Chen HC (1996) Classification and identification of nonrobust untestable path delay faults. IEEE Trans CAD Integr Circuits Syst 15(8):845–853

    Article  Google Scholar 

  8. Christou K, Michael MK, Tragoudas S (2008) On the use of ZBDDs for implicit and compact critical PDF test generation. J Electron Test 24(1-3):203–222

    Article  Google Scholar 

  9. Cruz R, Santhanam A (2003) Optimal routing, link scheduling and power control in multihop wireless networks. In: Proceedings of IEEE INFOCOM, vol 1, pp 702–711

  10. Drechsler R (2002) Evaluation of static variable ordering heuristics for MDD construction. In: Proceedings of international symposium on multiple-valued logic, pp 254–260

  11. Drechsler R, Gunther W, Somenzi F (2001) Using lower bounds during dynamic BDD minimization. IEEE Trans CAD Integr Circuits Syst 20(1):51–57

    Article  Google Scholar 

  12. Drechsler R, Shi J, Fey G (2004) Synthesis of fully testable circuits from BDDs. IEEE Trans CAD Integr Circuits Syst 23(3): 440–443

    Article  Google Scholar 

  13. Ebendt R, Drechsler R (2009) Approximate BDD minimization by weighted A. In: Proceedings of international symposium on circuits and systems, pp 2974–2977

  14. Ebendt R, Fey G, Drechsler R (2005) Advanced BDD optimization. Springer, Berlin

    Google Scholar 

  15. Friedman SJ, Supowit KJ (1987) Finding the optimal variable ordering for binary decision diagrams. In: Proceedings of international conference on CAD, pp 348–356

  16. Fujita M, Fujisawa H, Matsunaga Y (1993) Variable ordering algorithms for ordered binary decision diagrams and their evaluation. IEEE Trans CAD Integr Circuits Syst 12(1):6–12

    Article  Google Scholar 

  17. Gharaybeh MA, Bushnell ML, Agrawal VD (1998) The path-status graph with application to delay fault simulation. IEEE Trans CAD Integr Circuits Syst 17(4):324–332

    Article  Google Scholar 

  18. Gibbons A (1985) Algorithmic graph theory. Cambridge University Press, Cambridge

    MATH  Google Scholar 

  19. Goczyłla K, Cielatkowski J (1995) Optimal routing in a transportation network. Eur J Oper Res 87 (2):214–222

    Article  Google Scholar 

  20. Ishiura N, Sawada H, Yajima S (1991) Minimazation of binary decision diagrams based on exchanges of variables. In: Proceedings of international conference on CAD, vol 91, pp 472–475

  21. Iwasaki H, Minato SI, Zeugmann T (2007) A method of variable ordering for zero-suppressed binary decision diagrams in data mining applications. In: Proceedings of international workshop on databases for next generation researchers. IEEE, pp 85–90

  22. Iwashita H, Kawahara J, Minato SI (2012) ZDD-based computation of the number of paths in a graph. Hokkaido University, Division of Computer Science, TCS Technical Reports, vol TCS-TR-a-10-60

  23. Knuth DE (2009) The art of computer programming, vol 4, fascicles 0-4, 1st edn. Addison-Wesley Professional, Reading

    Google Scholar 

  24. Kocan F, Gunes M, Thornton MA (2004) Static variable ordering in ZBDDs for path delay fault coverage calculation. In: Proceedings of midwest symposium on circuits and systems, vol 1, pp 497–500

  25. Kocan F, Gunes MH (2005) On the ZBDD-based nonenumerative path delay fault coverage calculation. IEEE Trans CAD Integr Circuits Syst 24(7):1137–1143

    Article  Google Scholar 

  26. Kocan F, Li L, Saab DG (2009) Exact path delay fault coverage calculation of partitioned circuits. IEEE Trans Comput 58(6):858–864

    Article  MathSciNet  Google Scholar 

  27. Kurai R, Minato SI, Zeugmann T (2007) N-gram analysis based on zero-suppressed BDDs. In: Proceedings of new frontiers in artificial intelligence, pp 289–300

  28. Lenox J, Tragoudas S (2014) Adapting an implicit path delay grading method for parallel architectures. IEEE Trans CAD Integr Circuits Syst 33(12):1965–1976

    Article  Google Scholar 

  29. Li WN, Reddy SM, Sahni SK (1989) On path selection in combinational logic circuits. IEEE Trans CAD Integr Circuits Syst 8(1):56–63

    Article  Google Scholar 

  30. Michael MK, Tragoudas S (2005) Function-based compact test pattern generation for path delay faults. IEEE Trans Very Large Scale Integr Syst 13(8):996–1001

    Article  Google Scholar 

  31. Minato SI (1993) Zero-suppressed BDDs for set manipulation in combinatorial problems. In: Proceedings of conference on design automation, pp 272–277

  32. Mironov D, Ubar R, Raik J (2014) Logic simulation and fault collapsing with shared structurally synthesized BDDs. In: Proceedings of European test symposium, pp 1–2

  33. Neophytou S, Christou K, Michael MK (2012) A non-enumerative technique for measuring path correlation in digital circuits. J Electron Test 28(6):843–856

    Article  Google Scholar 

  34. Neophytou SN, Michael MK (2014) Optimal variable ordering in zbdd-based path representations for directed acyclic graphs. In: Proceedings of international conference on computer design, pp 489–492

  35. Nevo Z, Farkash M (2006) Distributed dynamic BDD reordering. In: Proceedings of design automation conference, pp 223–228

  36. Padmanaban S, Michael MK, Tragoudas S (2003) Exact path delay fault coverage with fundamental ZBDD operations. IEEE Trans CAD Integr Circuits Syst 22(3):305–316

    Article  Google Scholar 

  37. Panda S, Somenzi F (1995) Who are the variables in your neighbourhood. In: Proceedings of international conference on CAD, pp 74–77

  38. Qiu W, Walker D (2003) An efficient algorithm for finding the k longest testable paths through each gate in a combinational circuit. In: Proceedings of international test conference, pp 592–592

  39. Rudell R (1993) Dynamic variable ordering for ordered binary decision diagrams. In: Proceedings of international conference on CAD, pp 42–47

  40. Shah T, Matrosova A, Fujita M, Singh V (2018) Multiple stuck-at fault testability analysis of ROBDD based combinational circuit design. J Electron Test 34(1):53–65

    Article  Google Scholar 

  41. Shah T, Singh V, Matrosova A (2016) ROBDD Based path delay fault testable combinational circuit synthesis. In: Proceedings of east-west design & test symposium, pp 1–4

  42. Smith GL (1985) Model for delay faults based upon paths. In: Proceedings of international test conference, pp 342–351

  43. Somenzi F (1999) CUDD: CU decision diagram package. Dept. of ECE, The University of Colorando, Colorando

    Google Scholar 

  44. Ubar R, Jürimägi L, Raik J, Viies V (2017) Modeling and simulation of circuits with shared structurally synthesized BDDs. J Microprocess Microsys 48:56–61

    Article  Google Scholar 

  45. Wall DW (1991) Limits of instruction-level parallelism. In: Proceedings of international conference on architectural support for programming languages and operating systems, pp 176–188

  46. Wang LT, Chang YW, Cheng KTT (2009) Electronic design automation: synthesis, verification, and test. Morgan Kaufmann

  47. Yoon S, De Micheli G (2004) An application of zero-suppressed binary decision diagrams to clustering analysis of DNA microarray data. In: Proceedings of international conference of the IEEE engineering in medicine and biology society, vol 2, pp 2925–2928

Download references

Author information

Authors and Affiliations

  1. Engineering Department, University of Nicosia, P.O. Box 24005, Nicosia, CY-1700, Cyprus

    Stelios N. Neophytou

  2. Electrical and Computer Engineering Department and KIOS Research and Innovation Center of Excellence, University of Cyprus, Nicosia, Cyprus

    Maria K. Michael

Authors
  1. Stelios N. Neophytou
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Maria K. Michael
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Stelios N. Neophytou.

Additional information

Responsible Editor: S. Kajihara

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Neophytou, S.N., Michael, M.K. Path Representation in Circuit Netlists Using Linear-Sized ZDDs with Optimal Variable Ordering. J Electron Test 34, 667–683 (2018). https://doi.org/10.1007/s10836-018-5761-6

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10836-018-5761-6

Keywords

Search

Navigation