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High Performance Static Segment On-Chip Memory for Image Processing Applications

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Abstract

The performance of the processor core depends on the configuration parameters and utilization of on-chip memory in multimedia applications such as image, video and audio processing. The design of the on-chip memory architecture is critical for power and area efficient design without compromising quality in data-intensive computing applications. This paper proposes a design of high speed, area, and energy efficient Static Segment On-Chip (SSOC) memory for error-tolerant applications. In this static segment method, n-bit data array is reduced by m-bit data array for significant value of input data to achieve balanced design metrics at the cost of accuracy. The proposed m-bit static segmentation algorithm is implemented and verified in Single Port Static Random Access Memory (SP SRAM) architecture for the approximate computing applications. From the overall simulation results, the proposed 4-bit SSOC SP SRAM design provides 49.02% area savings, 50.62% power reduction and 16.92% speed improvement at the cost of 0.64% Peak Signal to Noise Ratio (PSNR) and exhibits same visual quality in comparison with the existing 8-bit conventional on-chip SP SRAM design in the image processing applications.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, KGiSL Institute of Technology, Coimbatore, India

    R. Jothin

  2. Department of Electronics and Communication Engineering, Government College of Technology, Coimbatore, India

    C. Vasanthanayaki

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  1. R. Jothin
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  2. C. Vasanthanayaki
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Correspondence to R. Jothin.

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Responsible Editor: S. Sindia

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Jothin, R., Vasanthanayaki, C. High Performance Static Segment On-Chip Memory for Image Processing Applications. J Electron Test 34, 389–404 (2018). https://doi.org/10.1007/s10836-018-5742-9

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  • DOI: https://doi.org/10.1007/s10836-018-5742-9

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