Gate Oxide Short Defect Model in FinFETs

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Abstract

FinFET technology is one of the most promising candidates in replacing planar MOSFET beyond the 22 nm technology node. However, the complexity of FinFET manufacturing process has caused challenges in reliable device testing. Gate oxide short (GOS) is one of the dominant defects that has significant impact on circuit reliability. In this paper, we present a GOS defect model for FinFETs by introducing the defect as a pinhole in the gate oxide of a triangular fin shape structure. The pinholes are represented by small cuboid cuts of various sizes on the fin top and sidewalls along the channel. The 3D Sentaurus TCAD simulation results in the development of an analytical GOS defect model that can be used in circuit-level fault modeling, which leads to generating more realistic test patterns.

Keywords

FinFET Gate oxide short Defect model Pinhole Leakage 

Notes

Acknowledgments

The authors would like to express their appreciation to Dr. Saman Adham for his valuable contribution and to CMC Microsystems and Synopsys Inc. for their support throughout this research.

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Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Department of ElectronicsCarleton UniversityOttawaCanada
  2. 2.Department of Electrical & Computer EngineeringRoyal Military CollegeKingstonCanada

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