Advertisement

Journal of Electronic Testing

, Volume 33, Issue 1, pp 25–36 | Cite as

A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits

  • I. Wali
  • B. Deveautour
  • Arnaud Virazel
  • A. Bosio
  • P. Girard
  • M. Sonza Reorda
Article

Abstract

Selecting the ideal trade-off between reliability and cost associated with a fault tolerant architecture generally involves an extensive design space exploration. Employing state-of-the-art reliability estimation methods makes this exploration un-scalable with the design complexity. In this paper we introduce a low-cost reliability analysis methodology that helps taking this key decision with less computational effort and orders of magnitude faster. Based on this methodology we also propose a selective hardening technique using a hybrid fault tolerant architecture that allows meeting the soft-error rate constraints within a given design cost-budget and vice versa. Our experimental validation shows that the methodology offers huge gain (1200 ×) in terms of computational effort in comparison with fault injection-based reliability estimation method and produces results within acceptable error limits.

Keywords

Fault tolerance Fault injection Susceptibility analysis Single event transient Permanent fault Delay fault Power consumption High dependability 

References

  1. 1.
    Asadi H and Tahoori MB. (2006) Soft error derating computation in sequential circuits. In: Computer-Aided Design, 2006. ICCAD ‘06. IEEE/ACM International Conference on. 2006, pp. 497–501. doi:  10.1109/ICCAD.2006.320164
  2. 2.
    Avižiens A (1976) Fault-Tolerant Systems. IEEE Trans Comput C-25(12):1304–1312 . doi: 10.1109/TC.1976.1674598 ISSN: 0018-9340CrossRefGoogle Scholar
  3. 3.
    Bottoni C, Coeffic B, Daveau JM, Naviner L and Roche P, (2015) Partial triplication of a sparc-v8 microprocessor using fault injection. Latin American Symposium on Circuits Systems, pp. 1–4Google Scholar
  4. 4.
    Fazeli M, Ahmadian S, Miremadi S, Asadi H, Tahoori M, (2011) Soft error rate estimation of digital circuits in the presence of multiple event transients (mets). Design Automation and Test in Europe Conference, pp. 1–6Google Scholar
  5. 5.
    Franco DT, Vasconcelos MC, Naviner L, and Naviner JF. (2008) Reliability analysis of logic circuits based on signal probability. In: Electronics, Circuits and Systems, ICECS 2008. 15th IEEE International Conference on. 2008, pp. 670–673. doi:  10.1109/ICECS.2008.4674942
  6. 6.
    Iniewski K. (2012) Advanced circuits for emerging technologies. Wiley, 2012. ISBN: 9781118181492. URL: https://books.google.fr/books?id=yuhbbtDFDtoC
  7. 7.
    Maniatakos M and Makris Y, (2010) Workload-driven selective hardening of control state elements in modern microprocessors. VLSI Test Symposium, pp. 159–164Google Scholar
  8. 8.
    Mohanram K and Touba N, (2013) Cost-effective approach for reducing soft error failure rate in logic circuits. International Test Conference, pp. 893–901Google Scholar
  9. 9.
    NanGate. (2011) Nangate 45 nm open cell library. [Online]. Available: http://www.nangate.com/?page id = 2325
  10. 10.
    Narasimham B et al (2007) Characterization of digital single event transient pulse-widths in 130-nm and 90-nm CMOS technologies. in IEEE Transactions on Nuclear Science 54(6):2506–2511. doi: 10.1109/TNS.2007.910125 CrossRefGoogle Scholar
  11. 11.
    Pagliarini SN, Naviner LAB and Naviner JF, (2012) Selective hardening methodology for combinational logic. Latin American Test Workshop, pp. 1–6Google Scholar
  12. 12.
    Polian I, Hayes J (2011) Selective hardening: toward cost-effective error tolerance. IEEE Des Test Comput 28(3):54–63CrossRefGoogle Scholar
  13. 13.
    Polian I, Reddy S, Becker B (2008) Scalable calculation of logical masking effects for selective hardening against soft errors. IEEE Computer Society Annual Symposium on VLSI, pp. 257–262Google Scholar
  14. 14.
    Shivakumar P, Kistler M, Keckler SW, Burger D, Alvisi L (2002) Modeling the effect of technology trends on the soft error rate of combinational logic. International Conference on Dependable Systems and Networks:389–398Google Scholar
  15. 15.
    Suge Yue, Xiaolin Zhang, Xinyuan Zhao, (2015) Single event transient pulse width measurement of 65-nm bulk CMOS circuits. J Semicond 36(11)Google Scholar
  16. 16.
    Tran DA, Virazel A, Bosio A, Dilillo L, Girard P, Todri A, Imhof M, Wunderlich HJ, (2012) A pseudo-dynamic comparator for error detection in fault tolerant architectures. VLSI Test Symposium, pp. 50–55Google Scholar
  17. 17.
    Wali I, Virazel A, Bosio A, Dilillo L, and Girard P, (2015a) An effective hybrid fault-tolerant architecture for pipelined cores. in Test Symposium (ETS), 2015 20th IEEE European, May 2015, pp. 1–6Google Scholar
  18. 18.
    Wali I, Virazel A, Bosio A, Girard P and Sonza Reorda M, (2015b) Design space exploration and optimization of a hybrid fault-tolerant architecture. On-LineTesting Symposium, pp. 89–94Google Scholar
  19. 19.
    Zoellin C, Wunderlich H, Polian I and Becker B, (2008) Selective hardening in early design steps. European Test Symposium, pp. 185–190Google Scholar

Copyright information

© Springer Science+Business Media New York 2017

Authors and Affiliations

  • I. Wali
    • 1
  • B. Deveautour
    • 1
  • Arnaud Virazel
    • 1
  • A. Bosio
    • 1
  • P. Girard
    • 1
  • M. Sonza Reorda
    • 2
  1. 1.Laboratoire d’Informatique, de Robotique et de Microélectronique de MontpellierUniversité de Montpellier / CNRS – UMR 5506 – CC477MontpellierFrance
  2. 2.Politecnico di TorinoTorinoItaly

Personalised recommendations