Journal of Electronic Testing

, Volume 33, Issue 1, pp 25–36 | Cite as

A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits

  • I. Wali
  • B. Deveautour
  • Arnaud Virazel
  • A. Bosio
  • P. Girard
  • M. Sonza Reorda


Selecting the ideal trade-off between reliability and cost associated with a fault tolerant architecture generally involves an extensive design space exploration. Employing state-of-the-art reliability estimation methods makes this exploration un-scalable with the design complexity. In this paper we introduce a low-cost reliability analysis methodology that helps taking this key decision with less computational effort and orders of magnitude faster. Based on this methodology we also propose a selective hardening technique using a hybrid fault tolerant architecture that allows meeting the soft-error rate constraints within a given design cost-budget and vice versa. Our experimental validation shows that the methodology offers huge gain (1200 ×) in terms of computational effort in comparison with fault injection-based reliability estimation method and produces results within acceptable error limits.


Fault tolerance Fault injection Susceptibility analysis Single event transient Permanent fault Delay fault Power consumption High dependability 


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Copyright information

© Springer Science+Business Media New York 2017

Authors and Affiliations

  • I. Wali
    • 1
  • B. Deveautour
    • 1
  • Arnaud Virazel
    • 1
  • A. Bosio
    • 1
  • P. Girard
    • 1
  • M. Sonza Reorda
    • 2
  1. 1.Laboratoire d’Informatique, de Robotique et de Microélectronique de MontpellierUniversité de Montpellier / CNRS – UMR 5506 – CC477MontpellierFrance
  2. 2.Politecnico di TorinoTorinoItaly

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