Advertisement

Journal of Electronic Testing

, Volume 32, Issue 4, pp 491–503 | Cite as

A New Approach for Modeling Inconsistencies in Digital-Assisted Analog Design

  • Gürkan Uygur
  • Sebastian M. Sattler
Article
  • 128 Downloads

Abstract

Safety critical circuits and systems require a specified function and real world structure to match each other. At the same time the functionality and the structure become more and more complex. This results in a high effort for design verification and test such that specification-oriented testing is getting more and more under pressure. In this paper we offer an approach to warrant the match between a specification and its structure by invertibly composing the corresponding “fingerprint” model. Conversely, the fingerprint warrants the match between specification and structure. We present a theoretical framework for creating the fingerprint from the specification and the structure, respectively, and demonstrate the parallel composition of fingerprints to an overall asynchronous feedback circuit system.

Keywords

Safety Structure Fingerprint Composition Asynchronous Feedback 

References

  1. 1.
    Automotive IC Market to Display Strongest Growth Through 2018, IC INSIGHTS (November 18, 2014). [Online]. Available: http://www.icinsights.com/data/articles/documents/736.pdf
  2. 2.
    Adámek J, Herrlich H, Strecker GE (2006) Abstract and concrete categories: the joy of cats. Repr Theory Appl Categ 17:1–507. reprint of the 1990 original [Wiley, New York]MathSciNetMATHGoogle Scholar
  3. 3.
    Berkel C. H. K. v., Josephs MB, Nowick SM (1999) Scanning the technology: Applications of asynchronous circuits. IEEE Proc 87(2):223–233CrossRefGoogle Scholar
  4. 4.
    Foty D, The future of Moore’s Law - Does it have one? (2015). In: International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) 2015Google Scholar
  5. 5.
    Foley C (1996) Characterizing metastability. In: Second International Symposium on Advanced Research in Asynchronous Circuits and Systems, 1996. Proceedings, pp 175–184Google Scholar
  6. 6.
    Gurkaynak F, Villiger T, Oetiker S, Felber N, Kaeslin H, Fichtner W (2002) A functional test methodology for globally-asynchronous locally-synchronous systems. In: Proceedings. Eighth International Symposium on Asynchronous Circuits and Systems, 2002, pp 181–189Google Scholar
  7. 7.
    Ginosar R (2011) Metastability and synchronizers: a tutorial. IEEE Des Test Comput 28(5):23–35CrossRefGoogle Scholar
  8. 8.
    Haydt M, Mourad S, Terry W, Terry J (2002) A new model for metastability. In: 9th International Conference on Electronics, Circuits and Systems, 2002, vol 1, pp 413–416Google Scholar
  9. 9.
    Hulgaard H, Burns SM, Borriello G (1995) Testing asynchronous circuits: a survey. Integr VLSI J 19 (3):111–131CrossRefMATHGoogle Scholar
  10. 10.
    International Technology Roadmap for Semiconductors, Design. (2005). [Online]. Available: www.itrs.net/Links/2005ITRS/Design2005.pdf
  11. 11.
    Khomenko V, Schaefer M, Vogler W, Wollowski R (2009) STG decomposition strategies in combination with unfolding. Acta Inform 46:433–474. [Online]. Available: http://dl.acm.org/citation.cfm?id=1669896.1669898 MathSciNetCrossRefMATHGoogle Scholar
  12. 12.
    Kurshan RP, McMillan KL (1991) Analysis of digital circuits through symbolic reduction. IEEE Trans CAD Integr Circ Syst 10(11):1356–1371. [Online]. Available: http://dblp.uni-trier.de/db/journals/tcad/tcad10.html#KurshanM91 CrossRefGoogle Scholar
  13. 13.
    Li D, Chuang P, Sachdev M (2010) Comparative analysis and study of metastability on high-performance flip-flops. In: 2010 11th International Symposium on Quality Electronic Design (ISQED), pp 853–860Google Scholar
  14. 14.
    Nowick S, Dill D (1995) Exact two-level minimization of hazard-free logic with multiple-input changes. IEEE Trans Comput-Aided Des Integr Circ Syst 14(8):986–997CrossRefGoogle Scholar
  15. 15.
    OMG, OMG Unified Modeling Language (OMG UML), Superstructure, Version 2.4.1, Object Management Group Std., Review 2.4.1, August 2011. [Online]. Available: http://www.omg.org/spec/UML/2.4.1
  16. 16.
    Shirvani P, Mitra S, Ebergen J, Roncken M (2000) DUDES: a fault abstraction and collapsing framework for asynchronous circuits. In: Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems, 2000. (ASYNC 2000) Proceedings, pp 73–82Google Scholar
  17. 17.
    Schaefer M Advanced STG Decomposition Books on Demand GmbH, 2008. [Online]. Available: http://books.google.de/books?id=GQMBvIqhyfkC
  18. 18.
    Shang DE University of Newcastle upon Tyne. School of Electrical, and C. Engineering, Asynchronous Communication Circuits: Design, Test and Synthesis. University of Newcastle upon Tyne, 2003. [Online]. Available: http://books.google.de/books?id=RZEEMwEACAAJ
  19. 19.
    Tang T (1991) Experimental studies of metastability behaviors of sub-micron CMOS ASIC flip flops. In: ASIC Conference and Exhibit, 1991. Proceedings., Fourth Annual IEEE International, pp P7–4/1–4Google Scholar
  20. 20.
    Uygur G, Sattler S (2015) Structure preserving modeling for safety critical systems. In: 2015 20th International Mixed-Signal Testing Workshop (IMSTW), pp 1–6Google Scholar
  21. 21.
    Xu Y (2011) Algorithms for automatic generation of relative timing constraints. Ph.D. Dissertation, UT, USAGoogle Scholar
  22. 22.
    Yoneda T, Kitai T, Myers CJ (2002) Automatic derivation of timing constraints by failure analysis. In: Brinksma E, Larsen KG (eds) CAV, Ser Lect Notes Comput Sci. [Online]. Available: http://dblp.uni-trier.de/db/conf/cav/cav2002.html#YonedaKM02, vol 2404. Springer, pp 195–208

Copyright information

© Springer Science+Business Media New York 2016

Authors and Affiliations

  1. 1.Chair of Reliable Circuits and SystemsUniversity of Erlangen-NurembergErlangenGermany

Personalised recommendations