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Journal of Electronic Testing

, Volume 32, Issue 3, pp 307–314 | Cite as

Impact of Fin-Height on SRAM Soft Error Sensitivity and Cell Stability

  • Hector Villacorta
  • Jaume Segura
  • Victor Champac
Article

Abstract

FinFET technology has become the most promising alternative to continue CMOS scaling due to its improved short channel effects. Design flexibility reduces on FinFET based circuits such as SRAM cells due to the effective channel width is determined by an integer number of fins. In this work, the impact of fin height size of FinFET transistors on the simultaneous behavior of soft error sensitivity and SRAM cell static noise margin is investigated. 3-D TCAD Sentarus environment is used to quantify the amount of collected and critical charges of an SRAM cell due to a heavy ion strike while Mix-Mode Hspice-TCAD simulation is used for stability analysis. Even more, the influence of process variations on sensitivity to soft errors and cell stability is considered. A 10 nm-SOI Tri-Gate FinFET technology is used. Results show that increasing the fin height of FinFET transistors considerably increases SRAM cell sensitivity to soft errors but improves its stability. This suggests that the optimum fin height value of FinFET transistors of an SRAM cell depends on the best tradeoff between soft error robustness and stability.

Keywords

FinFET Soft errors Static noise margin Process variations 

Notes

Acknowledgments

Hector Villacorta would like to thank CONACYT for the scholarship support under the postgraduate program with contract No. 212460. Jaume Segura acknowledges support from the Spanish Ministry of Economics and Competitivity and the Regional European Development funds (FEDER) from EU under project TEC2011-25017.

References

  1. 1.
    Baumann RC (2001) Soft errors in advanced semiconductor devices-part I: the three radiation sources. IEEE Trans Device Mater Reliab 1(1):17–22CrossRefGoogle Scholar
  2. 2.
    Brown AR, Idris NM, Watling JR, Asenov A (2010) Impact of metal gate granularity on threshold voltage variability: a full-scale three-dimensional statistical simulation study. IEEE Electron Device Letters 31(11):1199– 1201Google Scholar
  3. 3.
    Cannon EH, Gordon MS, Heidel DF, KleinOsowski AJ, Oldiges P, Rodbell KP, Tang H (2008) Multi-bit upsets in 65 nm SOI SRAMs. In: Proceedings of IEEE international reliability physics symposiumGoogle Scholar
  4. 4.
    Chen, M-C, Lin, C-H, Hou, Y-F,, Lin C-Y, Hsueh F-K, Liu H-L, Liu C-T, Wang B-W, Chen H-C, et al. (2013) A 10 nm si-based bulk FinFETs 6T SRAM with multiple fin heights technology for 25 % better Static Noise Margin. In: Proceedings of IEEE symposium on VLSI technology (VLSIT)Google Scholar
  5. 5.
    Fageeha O, Howard J, Block R (1994) Distribution of radial energy deposition around the track of energetic charged particles in silicon. J Appl Phys 75(5):2317–2321CrossRefGoogle Scholar
  6. 6.
    Fan M-L, Wu Y-S, Hu V-H, Su P, Chuang C-T (2009) Investigation of static noise margin of FinFET SRAM cells in sub-threshold regionGoogle Scholar
  7. 7.
    Fang Y-P, Oates AS (2011) Neutron-induced charge collection simulation of bulk FinFET SRAMs compared with conventional planar SRAMs. IEEE Trans Device Mater Reliab 11(4):551–554CrossRefGoogle Scholar
  8. 8.
    Hu V-H, Fan M-L, Su P, Chuang C-T (2010) Evaluation of static noise margin and performance of 6T FinFET SRAM cells with asymmetric gate to source/drain underlap devices. In: Proceedings IEEE international SOI conferenceGoogle Scholar
  9. 9.
    Johnson RA, Wichern DW (2014) Applied multivariate statistical analysis. PearsonGoogle Scholar
  10. 10.
    Lu DD, Dunga MV, Lin C-H, Niknejad AM, Hu C (2007) A multi-gate mosfet compact model featuring independent-gate operation. In: Proceedings of IEEE international electron devices meeting, pp 565–568Google Scholar
  11. 11.
    Lu DD (2011) Compact models for future generation CMOS. Ph.D. dissertation, University of California, BerkeleyGoogle Scholar
  12. 12.
    Montgomery DC, Runger GC (2010) Applied statistics and probability for engineers. WileyGoogle Scholar
  13. 13.
    Munteanu D, Autran J (2009) Transient response of 3-D Multi-Channel Nanowire MOSFETs submitted to heavy ion irradiation: a 3-D simulation study. IEEE Trans Nucl Sci 56(4):2042– 2049CrossRefGoogle Scholar
  14. 14.
    Qin J, Chen S, Chen J (2012) 3-D TCAD simulation study of the single event effect on 25 nm raised source-drain FinFET. Science China:1–5Google Scholar
  15. 15.
    Seevinck E, List FJ, Lohstroh J (1987) Static-noise margin analysis of mos sram cells. IEEE J Solid State Circuits 22(5):748–754CrossRefGoogle Scholar
  16. 16.
    Seifert N, Gill B, Jahinuzzaman S, Basile J, Ambrose V, Shi Q, Allmon R, Bramnik A (2012) Soft error Susceptibilities of 22 nm Tri-Gate devices. IEEE Trans Nucl Sci 59(6):2666– 2673CrossRefGoogle Scholar
  17. 17.
    Turowski M, Raman A, Xiong W (2011) Physics-based modeling of non planar Nanodevices (FinFETs) and their response to radiation. In: Proceedings of 18th IEEE international conference on mixed design of integrated circuits and systems, pp 460– 465Google Scholar
  18. 18.
    Wang X, Brown AR, Cheng B, Asenov A (2011) Statistical variability and reliability in nanoscale FinFETs. In: Proceedings of IEEE international electron devices meetingGoogle Scholar

Copyright information

© Springer Science+Business Media New York 2016

Authors and Affiliations

  • Hector Villacorta
    • 1
    • 2
  • Jaume Segura
    • 2
  • Victor Champac
    • 3
  1. 1.Polytechnic University of AguascalientesAguascalientesMexico
  2. 2.GSE-UIBUniversity of Balearic IslandsMallorcaSpain
  3. 3.National Institute for AstrophysicsOptics and Electronics (INAOE)TonantzintlaMexico

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