Journal of Electronic Testing

, Volume 32, Issue 3, pp 245–255 | Cite as

Optimization of Boundary Scan Tests Using FPGA-Based Efficient Scan Architectures

  • Igor Aleksejev
  • Sergei Devadze
  • Artur Jutman
  • Konstantin Shibin


This paper presents a method for optimization of board-level scan test with the help of reconfigurable scan-chains (RSCs) implemented in a programmable logic of FPGA. Despite that the RSC concept is a well-known solution for scan-based test time reduction, the usage of RSC may lead to un-acceptable hardware overhead. In our work, we are targeting a completely new approach of exploiting on-board FPGA resources that being unconfigured are typically available during the manufacturing test phase for carrying out tests using temporarily implemented virtual RSC structures. As the allocated FPGA logic is re-claimed for functional use after the test is finished, the presented method delivers all the advantages of RSCs at no extra hardware cost. Experimental results show that the proposed virtual RSCs can fit into all available commercial FPGAs providing a significant test time reduction in comparison with state-of-the-art Boundary Scan test tecnique.


Boundary Scan Reconfigurable Scan-Chain Embedded Instrumentation FPGA 



This work was supported by EU FP7-2013-ICT-11: 619871 project BASTION as well as through European Regional Development Fund.


  1. 1.
    Aleksejev I, Jutman A, Devadze S, Odintsov S, Wenzel T (2012) FPGA-based synthetic instrumentation for board test. In Proc. of International Test Conference, Austin, USACrossRefGoogle Scholar
  2. 2.
    Asset Intertech Inc., How to test high-speed memory with non-intrusive embedded instruments, Whitepaper, 2012.Google Scholar
  3. 3.
    Breuer MA, Narayanan S (1993) Reconfigurable Scan Chains, A Novel Approach to Reduce Test Application Time. In Proc. of International Conference on Computer-Aided Design, USAGoogle Scholar
  4. 4.
    Ehrenberg H, Russell B (2011) IEEE Std 1581 — a standardized test access methodology for memory devices. In Proc. of International Test Conference, Austin, USACrossRefGoogle Scholar
  5. 5.
    Escobar JHM, Sachße J, Ostendorff S, Wuttke H-D (2012) Automatic generation of an FPGA based embedded test system for printed circuit board testing. In Proc. of Latin American Test Workshop, Quito, EcuadorCrossRefGoogle Scholar
  6. 6.
    Ferry J, Scesnak J, Shaikh S (2005) A strategy for board level in-system programmable built-in assisted test and built-in self test. In Proc. of Internation Test Conference, Austin, USACrossRefGoogle Scholar
  7. 7.
    Geiger PB, Butkovich S (2009) Boundary-scan adoption – an industry snapshot with emphasis on the semiconductor industry. In Proc. International Test Conference, USACrossRefGoogle Scholar
  8. 8.
    Goepel GmbH., Cascon Galaxy System.Google Scholar
  9. 9.
    Guo C, Zhang Y, Wen Z, Chen L, Li X, Liu Z, Wang M (2011) A novel configurable boundary-scan circuit design of SRAM-based FPGA. In Proc. of Computer Science and Automation Engineering, ChinaGoogle Scholar
  10. 10.
    IEEE Standard test access port and boundary-scan architecture, 2001.Google Scholar
  11. 11.
    Intel Inc., Intel StrataFlash® Embedded Memory, Datasheet.Google Scholar
  12. 12.
    Intellitech Corp., Infrastructure IP for programming and test of in-system memory devices, Whitepaper, 2003.Google Scholar
  13. 13.
    Micron Technology Inc., Micron M25P32 Serial Flash Embedded Memory, Datasheet.Google Scholar
  14. 14.
    S. P. Morley et al. Selectable Length Partial Scan: a Method to Reduce Vector Length. in Proc. of Internation Test Conference, USA, 1991.Google Scholar
  15. 15.
    Nejedlo J, Khanna R (2009) Intel® IBIST, the full vision realized. In Proc. of International Test Conference, Santa Clara, USAGoogle Scholar
  16. 16.
    Parker KP (2003) The boundary-scan handbook. Kluwer Academic Publisher, Boston, MA, USA, p. 373CrossRefGoogle Scholar
  17. 17.
    Quasem S, Gupta S (2004) Designing reconfigurable multiple scan chains for systems-on-Chip. In Proc. of VLSI Test Symposium, USACrossRefGoogle Scholar
  18. 18.
    Samaranayake S, Sitchinava N, Kapur R, Amin MB, Williams TW (2002) Dynamic scan: driving down the cost of test. In IEEE Computer, OctoberGoogle Scholar
  19. 19.
    Spansion Inc., S29AL008D 8MBit Flash Memory, Datasheet.Google Scholar
  20. 20.
    Toai V, Zhiyuan W, Eaton T, Ghosh P, Huai L, Young L, Weili W, Rong F, Singletary D, Xinli G (2006) Design for Board and System Level Structural Test and diagnosis. In Proc. of International Test Conference, Santa Clara, USAGoogle Scholar
  21. 21.
    A. Tsertov, R. Ubar, A. Jutman, S. Devadze. SoC and Board Modeling for Processor-Centric Board Testing. In Proc. of 14th Euromicro Conference on Digital System Design, Oulu, Finland, 2011.Google Scholar
  22. 22.
    Wang S, Cao W, Wang L, Wang N, Tao P (2013) A novel structure of dynamic configurable scan chain bypassing unconcerned segments on the fly. In Proc. of International Conference on ASIC, ChinaGoogle Scholar
  23. 23.
    Wohl P, Waicukauski JA, Colburn JE (2012) Enhancing testability by structured partial scan. In Proc. of VLSI Test Symposium, USACrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 2016

Authors and Affiliations

  • Igor Aleksejev
    • 1
  • Sergei Devadze
    • 1
  • Artur Jutman
    • 2
  • Konstantin Shibin
    • 2
  1. 1.Tallinn Univ. of TechnologyTallinnEstonia
  2. 2.Testonica Lab OÜTallinnEstonia

Personalised recommendations