Journal of Electronic Testing

, Volume 31, Issue 5–6, pp 443–459 | Cite as

Phase Noise Testing of Analog/IF Signals Using Digital ATE: A New Post-Processing Algorithm for Extended Measurement Range

  • Stéphane David-Grignot
  • Florence Azaïs
  • Laurent Latorre
  • François Lefevre


This paper deals with low-cost phase noise testing of sinusoidal analog/IF signals. The idea is to perform over-sampled 1-bit signal acquisition using standard digital ATE and to apply dedicated post-processing in order to retrieve the phase noise level present in the analog/IF signal from the captured binary vector. A first algorithm has already been developed, which shows an excellent agreement with conventional phase noise measurements on a large range of injected noise but diverges from conventional method in case of very low phase noise level. In this paper, we present a new processing algorithm that permits to alleviate this limitation. Both simulations and hardware measurements are realized to validate the technique and results clearly demonstrate the improved performance of the new algorithm.


Analog signals Digital ATE Digital signal processing Noise measurement One bit acquisition Phase noise Analog/RF integrated circuits Test cost reduction 



This work has been carried out under the framework of ENIAC JU project “ELESIS: European Library-based flow of Embedded Silicon test Instruments”.


  1. 1.
    Angrisani L, Baccigalupi A, D’Arco M (2004) Evaluating phase noise power spectrum with variable frequency resolution. IEEE Trans Instrum Meas 53(3):685–691CrossRefGoogle Scholar
  2. 2.
    Angrisani L, D’apuzzo M, D’Arco M (2001) A digital signal-processing approach for phase noise measurement. IEEE Trans Instrum Meas 50(4):930–935CrossRefGoogle Scholar
  3. 3.
    Cai Y, Laquai B, Luehman K (2002) Jitter testing for gigabit serial communication transceivers. IEEE Des Test of Comput 19(1):66–74CrossRefGoogle Scholar
  4. 4.
    Choi H, Han D, Chatterjee A (2007) “Enhanced resolution jitter testing using jitter expansion”, Proc. IEEE VLSI Test Symposium (VTS) 104–109Google Scholar
  5. 5.
    Cosart LD, Peregrino L, Tambe A (1997) Time domain analysis and its practical application to the measurement of phase noise and jitter. IEEE Trans Instrum Meas 46(4):1016–1019CrossRefGoogle Scholar
  6. 6.
    David-Grignot S, Azais F, Latorre L, Lefevre F (2014) “Phase noise measurement on IF analog signals using standard digital ATE resources,” Proc. IEEE Int’l New Circ Syst Conf (NEWCAS) 121–124Google Scholar
  7. 7.
    David-Grignot S, Azais F, Latorre L, Lefevre F (2014) “Low-cost phase noise testing of complex RF ICs using standard digital ATE,” Proc IEEE Int’l Test Conf (ITC) paper 9.1Google Scholar
  8. 8.
    David-Grignot S, Azais F, Latorre L, Lefevre F (2014) “Stochastic model for phase noise measurement from 1-bit signal acquisition,” Proc IEEE Int’l Mixed-Sign, Sens Syst Test Workshop (IMS3TW) 1–6Google Scholar
  9. 9.
    Ecker A, Blakkan K, Soma M (2012) “A digital method for phase noise measurement,” Proc IEEE Int Test Conf (ITC) paper 2.2Google Scholar
  10. 10.
    Erdogan ES, Ozev S (2006) “A robust, self-tuning CMOS circuit for built-in Go/No-Go testing of synthesizer phase noise,” Proc IEEE Int Test Conf (ITC) paper 33.1Google Scholar
  11. 11.
    Feher K (1987) Telecommunications measurements, analysis and instrumentation. Prentice-Hall, Englewood CliffsGoogle Scholar
  12. 12.
    Grove J, Hein J, Retta J, Schweiger P, Solbrig W, Stein SR (2004) “Direct-digital phase-noise measurement,” Proc IEEE Int Freq Contrl Symp (IFCS) 287–291Google Scholar
  13. 13.
    Jae WL, Chun JH, Abraham JA (2009) “A random jitter RMS estimation technique for BIST applications,” Proc IEEE Asian Test Symp (ATS) 9–14Google Scholar
  14. 14.
    Keller MW, Kos AB, Silva TJ, Rippard WH, Pufall MR (2009) Time domain measurement of phase noise in a spin torque oscillator. Appl Phys Lett 94(19):193105–193105-3CrossRefGoogle Scholar
  15. 15.
    Khalil W, Bakkaloglu B, Kiaei S (2007) A self-calibrated on-chip phase-noise measurement circuit with −75 dBc single-tone sensitivity at 100 kHz offset. IEEE J Solid-State Circ 42(12):2758–2765CrossRefGoogle Scholar
  16. 16.
    Le Gall H, Alhakim R, Valka M, Mir S, Stratigopoulos H-G, Simeu E (2015) “High frequency jitter estimator for SoCs,” Proc. IEEE Europ Test Symp (ETS) 1–6Google Scholar
  17. 17.
    Lefevre F, Azais F, David-Grignot S, Latorre L (2015) “Method and apparatus for measuring phase noise,” Patent WO 2015/055823Google Scholar
  18. 18.
    Mendez-Rivera M, Silva-Martinez J, Sanchez-Sinencio E (2002) On-chip spectrum analyzer for built-in testing analog ICs. Proc IEEE Int Symp Circ Syst (ISCAS) 5:61–64Google Scholar
  19. 19.
    Ouda M, Hegazi E, Ragai HF (2009) “Digital on-chip phase noise measurement,” Proc Int Design Test Workshop (IDT) 1-5Google Scholar
  20. 20.
    Hewlett & Packard NJ (1985) Phase noise measurement seminar. Available:
  21. 21.
    Pous N, Azais F, Latorre L, Rivoir J (2010) “On the use of standard digital ATE for the analysis of RF signals,” Proc IEEE Europ Test Symp (ETS) 43–48Google Scholar
  22. 22.
    Rubiola E (2008) Phase noise and frequency stability in oscillators, Cambridge University Press (The Cambridge RF and microwave engineering series)Google Scholar
  23. 23.
    Su CC et al. (2004) “Dynamic analog testing via ATE digital test channels,” Proc IEEE Asian Test Symp (ETS) 308–312Google Scholar
  24. 24.
    Sunter S, Roy A (2004) On-chip digital jitter measurement, from megahertz to gigahertz. IEEE Des Test Comput 21(4):314–321CrossRefGoogle Scholar
  25. 25.
    Tabatabaei S, Ivanov A (2002) Embedded timing analysis: a SoC infrastructure. IEEE Des Test Comput 19(3):22–34CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • Stéphane David-Grignot
    • 1
    • 2
  • Florence Azaïs
    • 1
  • Laurent Latorre
    • 1
  • François Lefevre
    • 2
  1. 1.LIRMM, CNRS / Université MontpellierMontpellierFrance
  2. 2.NXP SemiconductorsCaenFrance

Personalised recommendations