Journal of Electronic Testing

, Volume 31, Issue 2, pp 207–215 | Cite as

A Shift-Register Based BIST Architecture for FPGA Global Interconnect Testing and Diagnosis

  • Igor Gadelha Pereira
  • Leonardo Alves Dias
  • Cleonilson Protásio de Souza


This paper describes the implementation of a shift-register based Built-In Self-Test (BIST) architecture for FPGA global interconnection resources testing. Through this, it is possible to configure FPGA resources that need to be tested in order to obtain high reliability FPGA-based systems. The proposed BIST approach takes advantage of FPGA low-level resources in order to generate cyclic test patterns, analyse testing response and store test results in a simple way. Additionally, the same BIST configuration set is capable of diagnosing the tested interconnection resources with no additional configurations thereby reducing time requirements. This paper presents the proposed BIST architecture and its diagnosis scheme, its implementation on a Xilinx FPGA, and experimental results.


Built-In Self-Test Field-Programmable Gate Array Global Interconnection Resource Testing FPGA Testing and Diagnosis 


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Copyright information

© Springer Science+Business Media New York 2015

Authors and Affiliations

  • Igor Gadelha Pereira
    • 1
  • Leonardo Alves Dias
    • 1
  • Cleonilson Protásio de Souza
    • 1
  1. 1.Departement of Electrical EngineeringFederal University of Paraíba - UFPBJoão PessoaBrazil

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