Advertisement

Journal of Electronic Testing

, Volume 30, Issue 2, pp 229–236 | Cite as

A Test Time Theorem and its Applications

  • Praveen Venkataramani
  • Suraj Sindia
  • Vishwani D. Agrawal
Article

Abstract

Power dissipated during test is a constraint when it comes to test time reduction. In this work, we show that for a given test the minimum test application time is achieved when the total energy is dissipated evenly at the rate of the maximum allowable power for the device under test. This result, the test time theorem, leads to two alternatives for reducing test time. In the first alternative, we scale the supply voltage down to reduce power, which in turn allows us to increase the clock frequency, of course within the limit imposed by the critical path. Thus, optimum voltage and frequency can be found to minimize the test time of a fixed frequency synchronous test. In the other alternative, which also benefits from the reduced voltage, the clock period is dynamically varied so that each cycle dissipates the maximum allowable power. This test, termed aperiodic clock test, according to the theorem achieves the lower bound on test time. An illustrative example of an ISCAS’89 benchmark circuit shows a test time reductionof 71 %.

Keywords

Aperiodic clock test Digital circuit testing Economics of testing Power constrained testing Test time reduction Voltage and frequency scaling 

Notes

Acknowledgment

This research is supported in part by the National Science Foundation Grants CNS-0708962, CCF-1116213 and IIP-0738088.

References

  1. 1.
    Agrawal V D (2012) Pre-Computed Asynchronous Scan (Invited Talk). In: 13th IEEE Latin American test workshop, QuitoGoogle Scholar
  2. 2.
    Agrawal V D (2012) Reduced voltage test can be faster. In Proceedings of international test conference. Elevator TalkGoogle Scholar
  3. 3.
    Bonhomme Y, Yoneda T, Fujiwara H, Girard P. (2004) An efficient scan tree design for test time reduction. In: Proceeding of 9th IEEE European test symposium, pp 174–179Google Scholar
  4. 4.
    Bushnell M L, Agrawal V D (2000) Essentials of electronic testing for digital, memory and mixed-signal VLSI circuits. Springer, BostonGoogle Scholar
  5. 5.
    Chalkia M, Tsiatouhas Y (2012) The leafs scan-chain for test application time and scan power reduction. In: Proceedings of 19th IEEE international conference electronics, circuits and systems, pp 749–752Google Scholar
  6. 6.
    Chang J T Y, McCluskey E J (1996) Detecting delay flaws by very-low-voltage testing. In: Proceedings of international test conference, pp 367–376Google Scholar
  7. 7.
    Chang J T Y, McCluskey E J (1996) Quantitative analysis of very-low-voltage testing. In: Proceeding of 14th IEEE VLSI test symposium, pp 332–337Google Scholar
  8. 8.
    Chloupek M, Novak O, Jenicek J (2012) On test time reduction using pattern overlapping, broadcasting and on-chip decompression. In: Proceedings IEEE 15th international symposium on design and diagnostics of electronic circuits systems (DDECS), pp 300–305Google Scholar
  9. 9.
    Chou R M, Saluja K K, Agrawal V D (1994) Power constraint scheduling of tests. In: Proceedings of 7th international conference VLSI design, pp 271–274Google Scholar
  10. 10.
    Chou R M, Saluja K K, Agrawal V D (1997) Scheduling tests for VLSI systems under power constraints. IEEE Trans VLSI Syst 5(2):175–185CrossRefGoogle Scholar
  11. 11.
    Daehn W, Mucha J (1981) Hardware test pattern generation for built-in testing. In: Proceeding of international test conference pp 110–120Google Scholar
  12. 12.
    Devanathan V R, Ravikumar C P, Mehrotra R, Kamakoti V (2007) PMScan: a power-managed scan for simultaneous reduction of dynamic and leakage power during scan test. In: Proceedings of IEEE international test conference, Paper 13.3Google Scholar
  13. 13.
    e Silva L G, Phillips J, Silveira L M (2010) Effective corner-based techniques for variation-aware IC timing verification. IEEE Trans Comput Aided Des Integr Circ Syst 29(1):157–162CrossRefGoogle Scholar
  14. 14.
    e Silva L G, Silveira L M, Phillips J R (2007) Efficient computation of the worst-delay corner. In: Proceedings of design, automation test in Europe conference exhibition, pp 1–6Google Scholar
  15. 15.
    Hao H, McCluskey E J (1993) Very-low-voltage testing for weak CMOS logic ICs. In: Proceedings of international test conference, pp 275–284Google Scholar
  16. 16.
    Hashempour H, Meyer F J, Lombardi F (2002) Test time reduction in a manufacturing environment by combining BIST and ATE. In: Proceedings of 17th IEEE international symposium on defect and fault tolerance in VLSI systems, pp 186–194Google Scholar
  17. 17.
    Lai W-J, Kung C-P, Lin C-S (1993) Test time reduction in scan designed circuits. In: Proceedings of 4th european conference on design automation, pp 489–493Google Scholar
  18. 18.
    Larsson E (2005) Introduction to advanced system-on-chip test design and optimization. Springer, DordrechtGoogle Scholar
  19. 19.
    Lin X, Press R, Rajski J, Reuter P, Rinderknecht T, Swanson B, Tamarapalli N (2003) High-frequency, At-Speed scan testing. IEEE Des Test Comput 20(5):17–25CrossRefGoogle Scholar
  20. 20.
    Pasricha S, Park Y-H, Kurdahi FJ, Dutt N (2008) Incorporating PVT variations in system-level power exploration of on-chip communication architectures. In: Proceedings of 21st international conference on VLSI design, pp 363–370Google Scholar
  21. 21.
    Ravi S (2007) Power-aware test: challenges and solutions. In: Proceedings of international test conference, pp 1–10Google Scholar
  22. 22.
    Razavi B (2002) Design of analog CMOS integrated circuits. McGraw-Hill, BostonGoogle Scholar
  23. 23.
    Sanghani A, Yang B, Natarajan K, Liu C (2011) Design and implementation of a time-division multiplexing scan architecture using serializer and deserializer in GPU chips. In: Proceedings of 29th IEEE VLSI test symposium, pp 219–224Google Scholar
  24. 24.
    Shanmugasundaram P., Agrawal V D (2011) Dynamic scan clock control for test time reduction maintaining peak power limit. In: Proceedings of 29th IEEE VLSI test symposium, pp 248–253Google Scholar
  25. 25.
    Shanmugasundaram P, Agrawal V D (2012) Externally tested scan circuit with built-in activity monitor and adaptive test clock. In: Proceedings of 25th international conference VLSI design, pp 448–453Google Scholar
  26. 26.
    Sheshadri V, Agrawal V D, Agrawal P (2012) Optimal power-constrained SoC test schedules with customizable clock rates. In: Proceedings of IEEE international SOC conference (SOCC), pp 271–276Google Scholar
  27. 27.
    Sheshadri V, Agrawal V D, Agrawal P (2013) Optimum test schedule for SoC with specified clock frequencies and supply voltages. In: Proceedings of 26th international conference VLSI design, pp 267–272Google Scholar
  28. 28.
    Sheshadri V, Agrawal V D, Agrawal P (2013) Power-aware SoC test optimization through dynamic voltage and frequency scaling. In: Proceedings of 21st IFIP/IEEE international conference very large scale integration (VLSI-SoC). Istanbul, pp 105–110Google Scholar
  29. 29.
    Venkataramani P (2014) Reducing ATE test time by voltage and frequency scaling. PhD thesis, Auburn University, ECE DepartmentGoogle Scholar
  30. 30.
    Venkataramani P, Agrawal V D (2012) Reducing ATE time for power constrained scan test by asynchronous clocking. In: Proceedings of IEEE international test conference, Poster P13Google Scholar
  31. 31.
    Venkataramani P, Agrawal V D (2012) Test-time reduction in ATE using asynchronous clocking. In: Proceedings of 6th IEEE international workshop on design for manufacturability and yield. PosterGoogle Scholar
  32. 32.
    Venkataramani P, Agrawal V D (2013) ATE test time reduction using asynchronous clock period. In: Proceedings of international test conference, Paper 15.3Google Scholar
  33. 33.
    Venkataramani P, Agrawal V D (2013) Reducing test time of power constrained test by optimal selection of supply voltage. In: Proceedings of 26th international conference on VLSI design, pp 273–278Google Scholar
  34. 34.
    Venkataramani P, Sindia S, Agrawal V D (2013) A test time theorem and its applications. In: Proceedings of 14th IEEE Latin American test workshop, pp 1–5Google Scholar
  35. 35.
    Venkataramani P, Sindia S, Agrawal V D (2013) Finding best voltage and frequency to shorten power-constrained test time. In: Proceedings of 31st IEEE VLSI test symposium, pp 19–24Google Scholar
  36. 36.
    Yang B, Sanghani A, Sarangi S, Liu C (2011) A clock-gating based capture power droop reduction methodology for At-Speed scan testing. In: Proceedings design, automation test in Europe conference and exhibition, pp 1–7Google Scholar

Copyright information

© Springer Science+Business Media New York 2014

Authors and Affiliations

  1. 1.Department of Electrical and Computer EngineeringAuburn UniversityAuburnUSA

Personalised recommendations