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A Test Time Theorem and its Applications

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Abstract

Power dissipated during test is a constraint when it comes to test time reduction. In this work, we show that for a given test the minimum test application time is achieved when the total energy is dissipated evenly at the rate of the maximum allowable power for the device under test. This result, the test time theorem, leads to two alternatives for reducing test time. In the first alternative, we scale the supply voltage down to reduce power, which in turn allows us to increase the clock frequency, of course within the limit imposed by the critical path. Thus, optimum voltage and frequency can be found to minimize the test time of a fixed frequency synchronous test. In the other alternative, which also benefits from the reduced voltage, the clock period is dynamically varied so that each cycle dissipates the maximum allowable power. This test, termed aperiodic clock test, according to the theorem achieves the lower bound on test time. An illustrative example of an ISCAS’89 benchmark circuit shows a test time reductionof 71 %.

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Acknowledgment

This research is supported in part by the National Science Foundation Grants CNS-0708962, CCF-1116213 and IIP-0738088.

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Author notes

  1. Suraj Sindia

    Present address: Intel Corporation, Hillsboro, OR, 97124USA, USA

Authors and Affiliations

  1. Department of Electrical and Computer Engineering, Auburn University, Auburn, AL, 36849, USA

    Praveen Venkataramani, Suraj Sindia & Vishwani D. Agrawal

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  1. Praveen Venkataramani
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  2. Suraj Sindia
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  3. Vishwani D. Agrawal
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Correspondence to Praveen Venkataramani or Suraj Sindia.

Additional information

Responsible Editor: L. M. B. Poehls

This research was first presented at 14th IEEE Latin–American Test Workshop, Cordoba, Argentina, April 2–5, 2013

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Venkataramani, P., Sindia, S. & Agrawal, V.D. A Test Time Theorem and its Applications. J Electron Test 30, 229–236 (2014). https://doi.org/10.1007/s10836-014-5447-7

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