Evaluating the Effectiveness of a Software-Based Technique Under SEEs Using FPGA-Based Fault Injection Approach
Nowadays, microprocessor-based system’s robustness under Single Event Effects (SEEs) represents a very important concern. A widely adopted solution to make a microprocessor-based system robust consists in modifying the application code by adding redundancy and fault tolerance capabilities. In this context, the main idea behind this paper is to evaluate a software-based technique named Optimized Embedded Signature Monitoring (OESM) using an FPGA-based fault injection technique, which is able to inject a high number of Single Event Upsets (SEUs) and Single Event Transients (SETs) in a short period of time. The obtained results demonstrated not only the increase of system’s robustness level, but also point out the remaining weak areas in the microprocessor-based system with respect to both types of SEEs.
KeywordsSoftware-based fault tolerance techniques FPGA-based fault injection SEU SET
- 4.Entrena L, Garcia-Valderas M, Fernandez-Cardenal R, Portela M, Lopez-Ongil C (2012) Soft error sensitivity evaluation of microprocessors by multilevel emulation-based fault injection. IEEE Trans Comp 61(3)Google Scholar
- 5.International Technology Roadmap for Semiconductors (2009) Edition (www.itrs.net)
- 9.PICmicro® 18C MCU Family, Reference Manual (2000) Microchip Technology Inc., ref. DS39500AGoogle Scholar
- 10.Vargas F, Rocha CA, Farina A, de Alecrim AA Jr (2007) Embedded signature monitoring based on profiling deployed software technique. IEEE Int East–west Des Test Symp, Yerevan, Armenia, pp. 230–236Google Scholar