Journal of Electronic Testing

, Volume 28, Issue 5, pp 615–623 | Cite as

On Chip Signal Generators for Low Overhead ADC BIST

  • Jingbo Duan
  • Bharath Vasan
  • Chen Zhao
  • Degang Chen
  • Randall Geiger


Testing of ADCs deeply embedded in SOCs is a significant challenge due to access limitations. ADC Built-in self-test (BIST) is considered a promising alternative to traditional test. This paper investigates implementation issues in adapting the stimulus error identification and removal (SEIR) algorithm, originally developed for production test, into a practical ADC BIST solution. Signal generators with very low transistor count and area consumption are presented. Extremely simple methods for generating small constant voltage level shifts are introduced and evaluated. Simulation results show that the generated signals, together with the level shifts, are able to test a 16-bit ADC to 16 bit accuracy levels. These results demonstrate that accurate BIST of deeply embedded analog and mixed-signal (AMS) blocks may be practically implemented on chip with very low overhead.


ADC test BIST Signal generator INL 


  1. 1.
    Azaïs F, Bernard S, Bertrand Y, Renovell M (2001) A low-cost BIST architecture for linear histogram testing of ADCs. J Electron Test Theory Appl 17:139–147CrossRefGoogle Scholar
  2. 2.
    Bult K (2009) “Embedded analog-to-digital converters”. Proc. IEEE ESSCIRC’09, Sep, pp 52–64Google Scholar
  3. 3.
    Chen H, Wang C, Su C (2002) “A self calibrated ADC BIST methodology”. IEEE VLSI Test Symposium, pp 117–122Google Scholar
  4. 4.
    Flores M, Negreiros M et al (2005) Low cost BIST for static and dynamic testing of ADCs. J Electron Test Theory Appl 21:283–290CrossRefGoogle Scholar
  5. 5.
    Huang JH, Liu ZH, Jeng MC, Ko PK, Hu C (1992) “A physical model for MOSFET output resistance”. In: IEDM Tech. Dig. pp 569–572Google Scholar
  6. 6.
    Jiang H, Olleta B, Chen D, Geiger RL (2007) Testing high-resolution ADCs with low-resolution/accuracy deterministic dynamic element matched DAC. IEEE Trans Instrum Meas 56:1753–1762CrossRefGoogle Scholar
  7. 7.
    Jin L, Chen D, Geiger RL (2007) SEIR linearity testing of precision A/D converters in nonstationary environments with center-symmetric interleaving. IEEE Trans Instrum Meas 56:1776–1785CrossRefGoogle Scholar
  8. 8.
    Jin L, Parthasarathy K, Kuyel T, Chen D, Geiger RL (2005) Accurte testing of analog-to-digital converters using low linearity signals with stimulus error identification and removal. IEEE Trans Instrum Meas 54:1188–1199CrossRefGoogle Scholar
  9. 9.
    Lee D et al (2004) “Code-width testing-based compact ADC BIST circuit”. IEEE Trans Circ Syst II 51:603–606CrossRefGoogle Scholar
  10. 10.
    Sunter S, Nagi N (1997) “A simplified polynomial–fitting algorithm for DAC and ADC BIST”. Proc. IEEE International Test Conference, pp 389–395Google Scholar
  11. 11.
    Toner MF, Roberts GW (1995) A BIST scheme for a SNR, gain tracking, and frequency response test of a sigma-delta ADC. IEEE Trans Circ Syst II 42:1–15CrossRefGoogle Scholar
  12. 12.
    Toner MF, Roberts GW (1996) “A frequency response, harmonic distortion, and intermodulation distortion test for BIST of a sigma-delta ADC”. IEEE Trans Circ Syst II 43:608–613CrossRefGoogle Scholar
  13. 13.
    Wen Y-C (2005) “A BIST scheme for testing analog-to-digital converters with digital response analyses”. IEEE 23rd VLSI Test Symp, pp 383–388Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2012

Authors and Affiliations

  • Jingbo Duan
    • 1
  • Bharath Vasan
    • 1
  • Chen Zhao
    • 1
  • Degang Chen
    • 1
  • Randall Geiger
    • 1
  1. 1.Department of Electrical and Computer EngineeringIowa State UniversityAmesUSA

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