Reliability Limits of TMR Implemented in a SRAM-based FPGA: Heavy Ion Measures vs. Fault Injection Predictions

  • Gilles Foucard
  • Paul Peronnard
  • Raoul Velazco


This paper presents experimental results putting in evidence the potential weaknesses of a state-of-the-art fault tolerance strategy, the Triple Modular Redundancy (TMR), when implemented in SRAM-based FPGAs. HW/SW fault injection campaigns and accelerated radiation ground tests were performed to quantify the number of faults, Single Event Upsets (SEUs) required to obtain such critical failures.


TMR FPGA SRAM SEUs Laser tests Fault injection Heavy ions 



Authors thanks Dr. Gary Swift from Xilinx Corporation for his support to the X-TMR version of the application, Dr. Vincent Pouget, from IMS/CNRS, for his support for laser test experiments and finally M. Guy Berger, from UCL, for his support will performing heavy ion ground testing.


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Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  1. 1.Laboratoire TIMAGrenobleFrance

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