An Optimized Seed-based Pseudo-random Test Pattern Generator: Theory and Implementation

  • Haijun Sun
  • Yongjia Zeng
  • Pu Li
  • Shaochong Lei
  • Zhibiao Shao


This paper presents a novel seed-based test pattern generator (SB-TPG). The core of SB-TPG is a seed sequence generator. A coverage-driven seed generation algorithm has been proposed to generate the optimized seeds. The test sequence generated by SB-TPG is a single input change (SIC) sequence that can significantly reduce test power for test-per-clock built-in self-test (BIST). Further, seed-masking technique has been put forward to filter those power-consuming seeds, thus reducing test power for test-per-scan BIST. Experimental results show that SB-TPG can achieve high fault coverage with short test length, low power and small hardware overhead.


Test pattern generator (TPG) Seed Single input change (SIC) sequence Built-in self-test (BIST) Fault coverage Low power 


  1. 1.
    Abramovici M, Breuer M, Freidman A (1990) Digital systems testing and testable design. Wiley-Interscience Publication.Google Scholar
  2. 2.
    Abu-Issa AS, Quigley SF (2009) Bit-swapping LFSR and scan-chain ordering: a novel technique for peak-and average-power reduction in scan-based BIST. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 28(5):755–759CrossRefGoogle Scholar
  3. 3.
    Basturkmen NZ, Reddy SM, Pomeranz I (Oct. 2002) Pseudo random patterns using Markov sources for scan BIST. In Proc. IEEE Test Symp., pp 1013–1021.Google Scholar
  4. 4.
    Bellos M, Bakalis D, Nikolos D (Feb. 2004) Scan cell ordering for low power BIST. In Proc. IEEE Computer society Annual Symp., pp 281–284.Google Scholar
  5. 5.
    Bhunia S, Mahmoodi H, Ghosh D, Mukhopadhyay S, Roy K (2005) Low-power scan design using first-level supply gating. IEEE Transactions on Very Large Scale Integration Systems 13(3):384–395CrossRefGoogle Scholar
  6. 6.
    Bhunia S, Mahmoodi H, Ghosh D, Roy K (Mar. 2005) Power reduction in test-per-scan BIST with supply gating and efficient scan partitioning. In Proc. Sixth International utality of Electronic Design Symp., pp 453-458.Google Scholar
  7. 7.
    Bhunia S, Mahmoodi H, Raychowdhury A, Roy K (Oct. 2004) First level hold: a novel low-overhead delay fault testing technique. 19th IEEE International Defect and Fault Tolerance in VLSI Systems Symp., pp 314-315.Google Scholar
  8. 8.
    Chaowen Y, Reddy SM, Pomeranz I (Nov. 2004) Weighted pseudo-random BIST for n-detection of single stuck-at faults. In IEEE Test Symp., pp 178–183.Google Scholar
  9. 9.
    Chen J-J, Yang C-K, Lee K-J (2003) Test pattern generation and clock disabling for simultaneous test time and power reduction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22(3):363–370CrossRefGoogle Scholar
  10. 10.
    Corno F, Rebaudengo M, Reorda MS, Squillero, Violante M (Apr. 2000) Low power BIST via non-linear hybrid cellular automata. In Proc. VLSI Testing Symp., pp 29–34.Google Scholar
  11. 11.
    Farooqi A, Gale RO, Reddy SM, Nutter B, Monico C (Mar. 2009) Markov source based test length optimized SCAN-BIST architecture. In Proc. IEEE Quality of Electronic Design Symp., pp 708–714.Google Scholar
  12. 12.
    Girard P (Mar. 2000) Low power testing of VLSI circuits: problems and solutions. In IEEE 2000 First International Symp., pp 173–179.Google Scholar
  13. 13.
    Girard P, Guiller L, Landrault C, Pravossoudovitch S (Apr. 1999) A test vector inhibiting technique for low energy BIST design. In Proc. IEEE VLSI Test Symp., pp 407–412.Google Scholar
  14. 14.
    Higami Y, Kobayashi S, Takamatsu Y, Kajihara S (Nov. 2004) Techniques for finding Xs in test sequences for sequential circuits and applications to test length/power reduction. In Proc. IEEE Test Symp., pp 46–49.Google Scholar
  15. 15.
    Huang XL, Huang JI (Jan. 2006) A routability constrained scan chain ordering technique for test power reduction. In Proc. Asia and South Pacific Design Automation Conf., pp 5.Google Scholar
  16. 16.
    Jas A, Krishna CV, Touba NA (2004) Weighted pseudorandom hybrid BIST. IEEE Transactions on Very Large Scale Integration Systems 12(12):1277–1283CrossRefGoogle Scholar
  17. 17.
    Lai N-C, Wang S-J, Fu Y-H (Nov. 2004) Low power BIST with smoother and scan-chain reorder. In Proc. Test Symp., pp 40–45.Google Scholar
  18. 18.
    Lee C-Y, Li C-M (Nov. 2005) Segment weighted random BIST (SWR-BIST): a low power BIST technique. In Proc. Asian Solid-State Circuits Conf., pp 333–336.Google Scholar
  19. 19.
    Lee H, Pomeranz I, Reddy SM (Mar. 2004) Scan BIST targeting transition faults using a Markov source. In Proc. IEEE Quality Electronic Design Symp., pp 497–502.Google Scholar
  20. 20.
    Li W, Yu C, Reddy SM, Pomeranz I (Jun. 2003) A scan BIST generation method using a Markov source and partial bit-fixing. In Proc. IEEE Design Automation Symp., pp 554–559.Google Scholar
  21. 21.
    Manich S, Gabarro A (May 1999) Low power BIST by filtering non-detecting vectors. In Proc. European Test Workshop, pp 165–170.Google Scholar
  22. 22.
    Nourani M, Tehranipoor M, Ahmed N (2008) Low-transition test pattern generation for BIST-based applications. IEEE Transactions on Computers 57(3):303–315MathSciNetCrossRefGoogle Scholar
  23. 23.
    Polian I, Becker B, Reddy SM (Jul. 2003) Evolutionary optimization of Markov sources for pseudo random scan BIST. In Proc. IEEE Automation and Test Symp., pp 1184–1185.Google Scholar
  24. 24.
    Tamarapalli N, Rajski J (Oct. 1996) Constructive multi-phase test point insertion for scan-based BIST. In Proc. IEEE International Test Conference, pp 649–658.Google Scholar
  25. 25.
    Touba N, McCluskey E (May 1996) Test point insertion based on path tracing. In IEEE VLSI Test Symp., pp 2–8.Google Scholar
  26. 26.
    Voyiatzis I, Efstathiou C (Mar. 2008) An efficient architecture for accumulator-based test generation of SIC pairs. DTIS 2008. 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era, pp 1–11.Google Scholar
  27. 27.
    Voyiatzis I, Haniotakis T, Halatsis C (Oct. 2006) Algorithm for the generation of SIC pairs and its implementation in a BIST environment. In IEE proc. Circuits, Devices and Systems, pp 427–432.Google Scholar
  28. 28.
    Waicukauski JS, Lindbloom E, Eichelberger EB, Forlenza OP (1989) WRP: a method for generating weighted random patterns. IBM Journal of Research and Development 33(2):149–161Google Scholar
  29. 29.
    Wang S (2007) A BIST TPG for low power dissipation and high fault coverage. IEEE Transactions on Very Large Scale Integration Systems 15(7):777–789CrossRefGoogle Scholar
  30. 30.
    Wang S, Chakradhar ST (2006) A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs. IEEE Transactions on Computer-Aided Design 25(8):1555–1564CrossRefGoogle Scholar
  31. 31.
    Wang S, Gupta SK (2002) DS-LFSR: a BIST TPG for switching activity. IEEE Transactions on Computer-Aided Design 21(7):842–851CrossRefGoogle Scholar
  32. 32.
    Xiang D, Chen M, Fujiwara H (2007) Using weighted scan enable signals to improve test effectiveness of scan-based BIST. IEEE Transactions on Computers 56(12):1619–1628MathSciNetCrossRefGoogle Scholar
  33. 33.
    Xiang D, Zhao Y, Chakrabarty K, Fujiwara H (2008) A reconfigurable scan architecture with weighted scan-enable signals for deterministic BIST. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27(6):999–1012CrossRefGoogle Scholar
  34. 34.
    Zhang X-D, Shan W, Roy K (2000) Low-power weighted random pattern testing. IEEE Transactions on Computer-Aided Design 19(11):1389–1398CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2011

Authors and Affiliations

  • Haijun Sun
    • 1
  • Yongjia Zeng
    • 2
  • Pu Li
    • 2
  • Shaochong Lei
    • 2
  • Zhibiao Shao
    • 2
  1. 1.School of Information EngineeringZhengzhou UniversityZhengzhouChina
  2. 2.Department of MicroelectronicsXi’an Jiao Tong UniversityXi’anChina

Personalised recommendations