Abstract
Scan-based Design-for-Testability technique is widely used to enhance the testability. However, it increases the vulnerability to attacks through scan chains for secure chips such as cryptographic circuits with embedded secret keys. This paper proposes a secure scan design method which protects the circuits containing secret information such as cryptographic circuits from scan-based side channel attacks. The proposed method prevents the leakage of secret information by partial scan design based on a balanced structure. We also guarantee the testability of both the design under test and DFT circuitry, and therefore, realize both security and testability. Experiments for RSA circuit shows the effectiveness of the proposed method.
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Responsible Editor: C. Metra
This work was supported in part by Japan Society for the Promotion of Science (JSPS) under Grants-in-Aid for Scientific Research ((B)20300018, (C)18500038).
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Inoue, M., Yoneda, T., Hasegawa, M. et al. Balanced Secure Scan: Partial Scan Approach for Secret Information Protection. J Electron Test 27, 99–108 (2011). https://doi.org/10.1007/s10836-011-5204-0
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DOI: https://doi.org/10.1007/s10836-011-5204-0