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Journal of Electronic Testing

, Volume 26, Issue 6, pp 679–688 | Cite as

Modified Selective Huffman Coding for Optimization of Test Data Compression, Test Application Time and Area Overhead

  • Usha Sandeep Mehta
  • Kankar S. Dasgupta
  • Nirnjan M. Devashrayee
Article

Abstract

A compression-decompression scheme, Modified Selective Huffman (MS-Huffman) scheme based on Huffman code is proposed in this paper. This scheme aims at optimization of the parameters that influence the test cost reduction: the compression ratio, on-chip decoder area overhead and overall test application time. Theoretically, it is proved that the proposed scheme gives the better test data compression compared to very recently proposed encoding schemes for any test set. It is clearly demonstrated with a large number of experimental results that the proposed scheme improves the test data compression, reduces overall test application time and on-chip area overhead compared to other Huffman code based schemes.

Keywords

IP core based SoC Huffman code Optimal selective Huffman code Test-data compression Test application time On-chip area-overhead 

Notes

Acknowledgment

The authors are thankful to Prof. Nur A. Tauba for providing MINTEST test sets for ISCAS89 benchmark circuits.

References

  1. 1.
    Chandra A, Chakrabarty K (2002) Reduction of SOC test data volume, scan power and testing time using alternating run-length codes. DAC ’02: Proceedings of the 39th conference on Design automation, June 2002, pp 673–678Google Scholar
  2. 2.
    Chandra A, Chakrabarty K (2003) Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length (FDR) codes. IEEE Transactions on Computers, vol. 52, Issue 8, August 2003, pp 1076–1088Google Scholar
  3. 3.
    El-Maleh A, Al-Abaji R (2002) Extended frequency-directed run-length code with improved application to system-on-a-chip test data compression. Proc. Int. Conf: on Electronics, Circuits and Systems, September 2002, 2:449–452Google Scholar
  4. 4.
    Feng J, Li G (2008) A test data compression method for system-on-a-chip. 4th IEEE International Symposium on Electronic Design, Test and Applications. DELTA 2008Google Scholar
  5. 5.
    Giri C, Rao B, Chattopadhyay S (2007) Test data compression by spilt-VIHC (SVIHC). ICCTA ’07: Proceedings of the International Conference on Computing: Theory and Applications, March 2007Google Scholar
  6. 6.
    Gonciari P, Al-Hashimi B, Nicolici N (2002) Improving compression ratio, area overhead, and test application time for system-on-a-chip test data compression/decompression. DATE '02: Proceedings of the conference on Design, automation and test in Europe, March 2002Google Scholar
  7. 7.
    Gonciari P, Al-Hashimi B, Nicolici N (2003) Variable-length input Huffman coding for system-on-a-chip test. IEEE Trans. on CAD, vol 22, Issue 6, June 2003, pp 783–796Google Scholar
  8. 8.
    Hellebrand S, Würtenberger A (2002) Alternating run-length coding—a technique for improved test data compression. Handouts 3rd IEEE International Workshop on Test Resource Partitioning, Baltimore, MD, USA, October 10–11, 2002Google Scholar
  9. 9.
    Jas A, Ghosh-Dastidar J, Touba NA (1999) ScanVector compression/decompression using statistical coding. In: Proc. VLSI Test Symp., pp 114–120Google Scholar
  10. 10.
    Jas A, Ghosh-Dastidar J, Ng M-E, Touba NA (2003) An efficient test vector compression scheme using selective Huffman coding. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol 22, Issue 6, June 2003Google Scholar
  11. 11.
    Kavousianos X, Kalligeros E, Nikolos D (2007) Optimal selective Huffman coding for test-data compression. IEEE Transactions on Computers, vol 56, Issue 8, August 2007Google Scholar
  12. 12.
    Kavousianos X, Kalligeros E, Nikolos D (2008) Multilevel-Huffman test-data compression for IP cores with multiple scan chains. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol 16, Issue 7, July 2008Google Scholar
  13. 13.
    Koenemann B et al (2001) A SmartBIST variant with guaranteed encoding. In: Proceedings of the Asian Test Symposium, pp 325–330Google Scholar
  14. 14.
    Li L, Chakrabarty K (2004) On using exponential—Golomb codes and subexponential codes for system-on-chip test data compression. Journal of Electronic Testing: Theory and Applications, vol 20, Issue 6, December 2004Google Scholar
  15. 15.
    Mehta U, Dasgupta K, Devashrayee N (2009) Frequency dependant bit appending: an enhancement to statistical codes for test data compression. Proceedings of the India Conference, NDICON’09, December 2009, pp 301–304Google Scholar
  16. 16.
    Mehta U, Devashrayee N, Dasgupta K (2009) Survey of test data compression techniques emphasizing code based scheme. In: Proceedings of IEEE 12th Euromicro Conference on Digital System Design (DSD09), August 09, pp 617–620Google Scholar
  17. 17.
    Mehta U, Dasgupta K, Devashrayee N (2010) Run length based test data compression techniques: how far from entropy and power bounds? Journal “VLSI Design” from Hindawi Publication CorporationGoogle Scholar
  18. 18.
    Nourani M, Tehranipour MH (2005) RL-Huffman encoding for test compression and power reduction in scan applications. Transactions on Design Automation of Electronic Systems (TODAES), vol 10, Issue 1, January 2005Google Scholar
  19. 19.
    Rajaski J et al (2002) Embedded deterministic test for low-cost manufacturing test. In: Proceedings of the International Test Conference, pp 301–310Google Scholar
  20. 20.
    Tauba N (2006) Survey of test vector compression techniques. IEEE transaction Design & Test of Computers, pp 294–303Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2010

Authors and Affiliations

  • Usha Sandeep Mehta
    • 1
  • Kankar S. Dasgupta
    • 2
  • Nirnjan M. Devashrayee
    • 1
  1. 1.Nirma UniversityAhmedabadIndia
  2. 2.Space Application CenterISROAhmedabadIndia

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