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Journal of Electronic Testing

, Volume 25, Issue 4–5, pp 213–223 | Cite as

Critical Path Selection for Delay Testing Considering Coupling Noise

  • Rajeshwary Tayade
  • Jacob A. Abraham
Article

Abstract

The objective of delay testing is to detect any defects or variations that manifest into timing failures. In path based delay testing this is done by testing a subset of paths in the circuit that are more likely to fail and hence are critical. Since path delays are vector dependent, the set of critical paths selected depends on the vectors assumed when estimating the path delays. This implies that to find the real critical paths, it is important to consider the effect of dynamic (vector dependent) delay effects such as coupling noise and supply noise during path selection. In this work a methodology to incorporate the effect of coupling noise during path selection is described. For any given path, both logic and timing constraints are extracted and a constrained optimization problem is formulated to estimate the maximum path delay in the presence of coupling noise.

Keywords

Delay testing Path selection Dynamic variations Coupling noise 

References

  1. 1.
    Agarwal K, Sato T, Cao Y, Slyvester D, Hu C (2003) Efficient generation of delay change curves for noise-aware static timing analysis. In: Proc. of 4th int. symposium of quality electronic design (ISQED)Google Scholar
  2. 2.
    Bai X, Dey S, Krstic A (2003) HyAC: a hybrid structural SAT based ATPG for crosstalk. In: International test conference, pp 112–121Google Scholar
  3. 3.
    Chen C-A, Gupta SK (1996) A satisfiability-based test generator for path delay faults incombinational circuits. In: Design automation conference, pp 209–214Google Scholar
  4. 4.
    Chen W, Gupta SK, Breuer MA (1998) Test generation in VLSI circuits for crosstalk noise. In: International test conference, pp 641–650Google Scholar
  5. 5.
    Cory BD, Kapur R, Underwood B (2003) Speed binning with path delay test in 150-nm technology. IEEE Des Test Comput 20:41–45CrossRefGoogle Scholar
  6. 6.
    Friedman JH (1991) Multivariate adaptive regression splines. Ann Stat 19:1–14MATHCrossRefGoogle Scholar
  7. 7.
    Fu Z, Malik S (2006) Solving the minimum-cost satisfiability problem using SAT based branch-and-bound search. In: ICCAD, pp 852–859Google Scholar
  8. 8.
    Hashempour H, Kim Y-B, Park N (2002) A test-vector generation methodology for crosstalk noise faults. In: Defect and fault tolerance, pp 40–47Google Scholar
  9. 9.
    Irajpour S, Gupta SK, Breuer MA (2004) Timing-independent testing of crosstalk in the presence of delay producing defects using surrogate fault models. In: International Test Conference, pp 1024–1033Google Scholar
  10. 10.
    Krstic A, Liou J-J, Jiang Y-M, Cheng K-T (2001) Delay testing considering crosstalk-induced effects. In: International test conference, pp 558–567Google Scholar
  11. 11.
    Kulkarni M, Chen T (2004) A sensitivity based approach to analyzing signal delay uncertainty of coupled interconnects. In: Proc. of 5th int. symposium of quality electronic design (ISQED), pp 331–336Google Scholar
  12. 12.
    Li H, Shen P, Li X (2006) Robust test generation for precise crosstalk-induced path delay faults. In: VLSI test symposium, pp 300–305Google Scholar
  13. 13.
    Lu X, Li Z, Qiu W, Walker D, Shi W (2004) Longest path selection for delay test under process variation. In: ASPDAC, pp 98–103Google Scholar
  14. 14.
    Mahajan YS, Fu Z, Malik S (2005) Zchaff2004: an efficient SAT solver. In: SAT 2004, LNCS, vol. 3542, pp 360–375Google Scholar
  15. 15.
    Majhi A, Jacob J, Patnaik L, Agrawal V (1996) On test coverage of path delay faults. In: International test conference, pp 418–421Google Scholar
  16. 16.
    Shen P-F, Li H-W, Xu Y-J, Li X-W (2005) Non-robust test generation for crosstalk-induced delay faults. In: Asian test symposium, pp 120–125Google Scholar
  17. 17.
    Tani S, Teramoto M, Fukazawa T, Matsuhiro K (1998) Efficient path selection for delay testing based on partial path evaluation. In: VLSI test symposiumm, pp 188–193Google Scholar
  18. 18.
    Tayade R, Kalyanam V, Nassif S, Abraham JA (2007) Estimating path delay distribution considering coupling noise. In: ACM GLSVLSI, pp 61–66Google Scholar
  19. 19.
    Wang L-C, Liou J-J, Cheng K-T (2004) Critical path selection for delay fault testing based upon a statistical timing model. IEEE Trans Comput Aided Des 23:1550–1564CrossRefGoogle Scholar
  20. 20.
    Wangqi Q, Walker DMH (2003) An efficient algorithm for finding the k longest testable paths through each gate in a combinational circuit. In: International test conference, pp 592–601Google Scholar
  21. 21.
    Zhao J-K, Rudnick EM, Patel JH (1997) Static logic implication with application to redundancy identification. In: VLSI test symposium, pp 288–293Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2009

Authors and Affiliations

  1. 1.University of Texas at AustinAustinUSA

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