Abstract
The objective of delay testing is to detect any defects or variations that manifest into timing failures. In path based delay testing this is done by testing a subset of paths in the circuit that are more likely to fail and hence are critical. Since path delays are vector dependent, the set of critical paths selected depends on the vectors assumed when estimating the path delays. This implies that to find the real critical paths, it is important to consider the effect of dynamic (vector dependent) delay effects such as coupling noise and supply noise during path selection. In this work a methodology to incorporate the effect of coupling noise during path selection is described. For any given path, both logic and timing constraints are extracted and a constrained optimization problem is formulated to estimate the maximum path delay in the presence of coupling noise.
Similar content being viewed by others
References
Agarwal K, Sato T, Cao Y, Slyvester D, Hu C (2003) Efficient generation of delay change curves for noise-aware static timing analysis. In: Proc. of 4th int. symposium of quality electronic design (ISQED)
Bai X, Dey S, Krstic A (2003) HyAC: a hybrid structural SAT based ATPG for crosstalk. In: International test conference, pp 112–121
Chen C-A, Gupta SK (1996) A satisfiability-based test generator for path delay faults incombinational circuits. In: Design automation conference, pp 209–214
Chen W, Gupta SK, Breuer MA (1998) Test generation in VLSI circuits for crosstalk noise. In: International test conference, pp 641–650
Cory BD, Kapur R, Underwood B (2003) Speed binning with path delay test in 150-nm technology. IEEE Des Test Comput 20:41–45
Friedman JH (1991) Multivariate adaptive regression splines. Ann Stat 19:1–14
Fu Z, Malik S (2006) Solving the minimum-cost satisfiability problem using SAT based branch-and-bound search. In: ICCAD, pp 852–859
Hashempour H, Kim Y-B, Park N (2002) A test-vector generation methodology for crosstalk noise faults. In: Defect and fault tolerance, pp 40–47
Irajpour S, Gupta SK, Breuer MA (2004) Timing-independent testing of crosstalk in the presence of delay producing defects using surrogate fault models. In: International Test Conference, pp 1024–1033
Krstic A, Liou J-J, Jiang Y-M, Cheng K-T (2001) Delay testing considering crosstalk-induced effects. In: International test conference, pp 558–567
Kulkarni M, Chen T (2004) A sensitivity based approach to analyzing signal delay uncertainty of coupled interconnects. In: Proc. of 5th int. symposium of quality electronic design (ISQED), pp 331–336
Li H, Shen P, Li X (2006) Robust test generation for precise crosstalk-induced path delay faults. In: VLSI test symposium, pp 300–305
Lu X, Li Z, Qiu W, Walker D, Shi W (2004) Longest path selection for delay test under process variation. In: ASPDAC, pp 98–103
Mahajan YS, Fu Z, Malik S (2005) Zchaff2004: an efficient SAT solver. In: SAT 2004, LNCS, vol. 3542, pp 360–375
Majhi A, Jacob J, Patnaik L, Agrawal V (1996) On test coverage of path delay faults. In: International test conference, pp 418–421
Shen P-F, Li H-W, Xu Y-J, Li X-W (2005) Non-robust test generation for crosstalk-induced delay faults. In: Asian test symposium, pp 120–125
Tani S, Teramoto M, Fukazawa T, Matsuhiro K (1998) Efficient path selection for delay testing based on partial path evaluation. In: VLSI test symposiumm, pp 188–193
Tayade R, Kalyanam V, Nassif S, Abraham JA (2007) Estimating path delay distribution considering coupling noise. In: ACM GLSVLSI, pp 61–66
Wang L-C, Liou J-J, Cheng K-T (2004) Critical path selection for delay fault testing based upon a statistical timing model. IEEE Trans Comput Aided Des 23:1550–1564
Wangqi Q, Walker DMH (2003) An efficient algorithm for finding the k longest testable paths through each gate in a combinational circuit. In: International test conference, pp 592–601
Zhao J-K, Rudnick EM, Patel JH (1997) Static logic implication with application to redundancy identification. In: VLSI test symposium, pp 288–293
Author information
Authors and Affiliations
Corresponding author
Additional information
Responsible Editor: C. Metra
Rights and permissions
About this article
Cite this article
Tayade, R., Abraham, J.A. Critical Path Selection for Delay Testing Considering Coupling Noise. J Electron Test 25, 213–223 (2009). https://doi.org/10.1007/s10836-009-5105-7
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10836-009-5105-7