Journal of Electronic Testing

, Volume 24, Issue 4, pp 353–364 | Cite as

A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction

  • N. Badereddine
  • Z. Wang
  • P. Girard
  • K. Chakrabarty
  • A. Virazel
  • S. Pravossoudovitch
  • C. Landrault


Scan architectures, though widely used in modern designs for testing purpose, are expensive in test data volume and power consumption. To solve these problems, we propose in this paper to modify an existing test data compression technique (Wang Z, Chakrabarty K in Test data compression for IP embedded cores using selective encoding of scan slices. IEEE International Test Conference, paper 24.3, 2005) so that it can simultaneously address test data volume and power consumption reduction for scan testing of embedded Intellectual Property (IP) cores. Compared to the initial solution that fill don’t-care bits with the aim of reducing only test data volume, here the assignment is performed to minimize also the power consumption. The proposed power-aware test data compression technique is applied to the ISCAS’89 and ITC’99 benchmark circuits and on a number of industrial circuits. Results show that up to 14× reduction in test data volume and 98% test power reduction can be obtained simultaneously.


DfT Scan Low power testing Test data compression 


  1. 1.
    Al-Yamani A, Chmelar E, Grinchuck M (2005) Segmented addressable scan architecture. IEEE VLSI Test Symposium, pp 405–411Google Scholar
  2. 2.
    Badereddine N, Girard, Pravossoudovitch S, Landrault C, Virazel A, Wunderlich H-J (2006) Structural power-aware assignment of don’t cares for peak power reduction during scan testing. IFIP International Conference on Very Large Scale Integration, pp 403–408Google Scholar
  3. 3.
    Baik DH, Saluja KK (2005) Progressive random access scan: a simultaneous solution to test power, test data volume and test time. IEEE International Test Conference, paper 15.2Google Scholar
  4. 4.
    Bayraktaroglu I, Orailoglu A (2003) Decompression hardware determination for test volume and time reduction through unified test pattern compaction and compression. IEEE VLSI Test Symposium, pp 113–118Google Scholar
  5. 5.
    Bushnell ML, Agrawal VD (2000) Essentials of electronic testing. Kluwer Academic PublishersGoogle Scholar
  6. 6.
    Butler KM, Saxena J, Fryars T, Hetherington G (2004) Minimizing power consumption in scan testing: pattern generation and DFT techniques. IEEE International Test Conference, pp 355–364Google Scholar
  7. 7.
    Chandra A, Chakrabarty K (2001) Combining low-power scan testing and test data compression for system-on-a-chip. Design Automation Conference, pp 166–171Google Scholar
  8. 8.
    Chandramouli M (2003) How to implement deterministic logic Built-in Selftest (BIST). Compiler: A Monthly magazine for technologies worldwide, Synopsys, JanuaryGoogle Scholar
  9. 9.
    Girard P (2002) Survey of low-power testing of VLSI circuits. IEEE Des Test Comput 19(3):82–92 May–JuneCrossRefMathSciNetGoogle Scholar
  10. 10.
    Hamzaoglu I, Patel J (1999) Reducing test application time for full scan embedded cores. IEEE International Symposium on Fault Tolerant Computing, pp 206–267Google Scholar
  11. 11.
    Khoche A, Rivoir J (2000) I/O bandwith bottleneck for test: is it real? Test Resource Partitioning WorkshopGoogle Scholar
  12. 12.
    Koenemann B, Barnhart C, Keller B, Snethen T, Farnsworth O, Wheater D (2001) A SmartBIST variant with guaranteed encoding. IEEE Asian Test Symposium, pp 325–330Google Scholar
  13. 13.
    Nicolici N, Al-Hashimi B (2003) Power-constrained testing of VLSI circuits.. Springer, BerlinGoogle Scholar
  14. 14.
    Rajski J, Tyszer J, Kassab M, Mukherjee N (2004) Embedded deterministic test. IEEE Trans. on CAD 23:776–792 MayGoogle Scholar
  15. 15.
    Remersaro S, Lin X, Zhang Z, Reddy SM, Pomeranz I, Rajski J (2005) Preferred fill: a scalable method to reduce capture power for scan based designs. IEEE International Test Conference, paper 32.2Google Scholar
  16. 16.
    Rosinger P, Gonciari T, Al-Hashimi B, Nicolici N (2001) Simultaneous reduction in volume of test data and power dissipation for systems-on-a-chip. IEE Electronics Letters 37(24):1434–1436 NovemberCrossRefGoogle Scholar
  17. 17.
    Rosinger P, Al-Hashimi B, Nicolici N (2004) Scan architecture with mutually exclusive scan segment activation for shift and capture power reduction. IEEE Transactions on Computer Aided Design 23(7)::1142–1153 JulyCrossRefGoogle Scholar
  18. 18.
    Sankaralingam R, Oruganti RR, Touba NA (2000) Static compaction techniques to control scan vector power dissipation. IEEE VLSI Test Symposium, pp. 35–40Google Scholar
  19. 19.
    Saxena J, Butler KM, Jayaram VB, Kunduv, Arvind NV, Sreeprakash P, Hachinger M (2003) A case study of IR-Drop in structured at-speed testing. IEEE International Test Conference, pp. 1098–1104Google Scholar
  20. 20.
    Semiconductor Industry Association (2005) International Technology Roadmap for Semiconductors (ITRS)Google Scholar
  21. 21.
    Shi C et al (2004) How power aware test improves reliability and yield., September 15thGoogle Scholar
  22. 22.
    TetraMAX™ (2005) Version 2005.09, Synopsys IncGoogle Scholar
  23. 23.
    Vranken H, Hapke F, Rogge S, Chindamo D, Volkerink E (2003) ATPG Padding and ATE vector repeat per port for reducing test data volume. IEEE International Test Conf. pp. 1069–1076Google Scholar
  24. 24.
    Wang Z, Chakrabarty K (2005) Test data compression for IP embedded cores using selective encoding of scan slices. IEEE International Test Conference, paper 24.3Google Scholar
  25. 25.
    Wen X, Suzuki T, Kajihara S, Miyase K, Minamoto Y, Wang L-T, Saluja KK (2005) Efficient test set modification for capture power reduction. ASP Journal of Low Power Electronics 1(3):319–330 DecemberCrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2007

Authors and Affiliations

  • N. Badereddine
    • 1
  • Z. Wang
    • 2
  • P. Girard
    • 1
  • K. Chakrabarty
    • 2
  • A. Virazel
    • 1
  • S. Pravossoudovitch
    • 1
  • C. Landrault
    • 1
  1. 1.Laboratoire d’Informatique, de Robotique et de Microélectronique de MontpellierUniversité de Montpellier II/CNRSMontpellier Cedex 5France
  2. 2.Department of Electrical and Computer EngineeringDuke UniversityDurhamUSA

Personalised recommendations