Abstract
This paper presents simulations of three different implementations of the minority-3 function, with special focus on mismatch analysis through statistical Monte Carlo-simulations. The simulations clearly favors the minority-3 Mirrored gate, and a gate-level redundancy scheme, where identical circuits with the same input drive the same output-node, is further explored as a means of increasing fault- and defect-tolerance. Important trade-offs between supply voltage, redundancy and yield are revealed, and V DD = 175 mV is suggested as a minimum useful operating voltage, combined with a redundancy factor of 2, in 90 nm CMOS.
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References
Andreou AG, Boahen KA, Pouliquen PO, Pavasović A, Jenkins RE, Strohbehn K (1991) Current-mode subthreshold MOS circuits for analog VLSI neural systems. IEEE Trans Neural Netw 2(2):205–213, March
Aunet S, Beiu V (2005) Ultra low power fault tolerant neural inspired CMOS logic. IEEE International Joint Conference on Neural Networks, IJCNN, Montréal, Canada, July 31–August 4, 2005
Aunet S, Berg Y (2005) Three sub-fJ power-delay-product subthreshold CMOS gates. IFIP VLSI SoC, Perth, Australia, 17–19 October 2005
Aunet S, Hartmann M (2003) Real-time reconfigurable linear threshold elements and some applications to neural hardware. International Conference on Evolvable Systems, ICES 2003, Trondheim, Norway, 17–20 March 2003
Aunet S, Oelmann B, Abdalla S, Berg Y (2004) Reconfigurable subthreshold CMOS perceptron. International Joint Conference on Neural Networks, IJCNN, Budapest, Hungary, 25–29 July 2004
Beiu V, Aunet S, Rydberg III RR, Djupdal A (2005) On the advantages of serial architectures for low-power reliable computations. Proceedings of the 16th International Conference on Application-Specific Systems, Architecture and Processors, ASAP’05, Samos, Greece, 23–25 July 2005
Bryant A, Brown J, Cottrell P, Ketchen M, Ellis-Monaghan J, Nowak EJ (2001) Low-Power CMOS at Vdd=4kT/q. Dev Res Conf 2001
Closing the nanometer yield chasm, cadence design systems. White Paper, 2001. Available: www.cadence.com/whitepapers/ClosingNanometer061301.pdf
Eisele M, Berthold J, Schmitt-Landsiedel D, Mahnkopf R (1997) The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits. IEEE Transactions Very Large Scale Integr (VLSI) Syst 5(4):360–368, December
Enz CC, Krummenacher F, Vittoz EA (1995) An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications. Analog Integr Circuits Signal Process 8:83–114, July
Enz CC, Vittoz EA (1996) CMOS low-power analog circuit design. In: Cavin et al (eds) Emerging technologies: designing low power digital systems. IEEE Press
Granhaug K, Aunet S, Lande TS (2006) Body-bias regulator for ultra low power multifunction CMOS gates. International Symposium of Circuits and Systems, ISCAS 2006, Kos, Greece, 21–24 May 2006
Iwamura H, Akazawa M, Amemiya Y (1998) Single electron majority logic circuits. IEICE Transac Electron, V E18 C, pp 42–48
Kao JT, Miyazaki M, Chandrakasan AP (2002) A 175-mV multiply-accumulate unit using an adaptive supply voltage and body bias architecture. IEEE J Solid-State Circuits 37(11):1545–1554, November 2002
Lehtonen T, Plosila J, Isoaho J (2005) On fault tolerance techniques towards nanoscale circuits and systems. TUCS Technical Report, no. 708, August 2005
Leuenberger F, Vittoz E (1969) Complementary-MOS low-power low-voltage integrated binary counter. Proceedings of the IEEE 57(9):1528–1532, September
Lin X, Rajski J (2006) The impacts of untestable defects on transition fault testing. Proceedings of the 24th IEEE VLSI Test Symposium, VTS’06, Berkeley, CA, USA, 30 April–4 May 2006
Melek LAP, Schneider MC, Galup-Montoro C (2004) Body-bias compensation technique for subthreshold CMOS static logic gates. SBCCI’04, Ipojuca, Brazil, 7–11 September 2004
Moore G (1965) Cramming more components onto integrated circuits. Electronics 38(8):114–117
Nikolić K, Sadek A, Forshaw M (2002) Fault-tolerant techniques for nanocomputers. Nanotechnology 13:357–362, June
Nowak EJ (2002) Maintaining the benefits of CMOS scaling when scaling bogs down. IBM J Res Dev 46(2/3):169–180, March/May
Rabaey J, Pedram M, Landman P (1995) Low power design methodologies. Kluwer, Boston, 1995
Schmid A, Leblebici Y (2003) Robust circuit and system design methodologies for nanometer-scale devices and single-electron transistors. Third IEEE Conference on Nanotechnology, IEEE-NANO, San Francisco, CA, USA, 12–14 August 2003
Schrom G, Selberherr S (1996) Ultra-low-power CMOS technologies. International Semiconductor Conference, CAS’96, Sinaia, Romania
Schultz K, Francis RJ, Smith KC (1990) Ganged CMOS: trading standby power for speed. IEEE J Solid-State Circuits 25(3):870–873, June
Shibata T, Ohmi T (1991) An intelligent MOS transistor featuring gate-level weighted sum and threshold operations. Technical Digest of International Electron Devices Meeting, pp 919–922
Soeleman H, Roy K, Paul, BC (2001) Robust subthreshold logic for ultra-low power operation. IEEE Transac Very Large Scale Integr (VLSI) Syst 9(1):90–99, Febuary
Swanson RM, Meindl JD (1972) Ion-implanted complementary MOS transistors in low-voltage circuits. IEEE J Solid-State Circuits 7(2):146–153, April
von Neumann J (1956) Probabilistic logics and the synthesis of reliable organisms from unreliable components. In: Shannon CE, McCarthy J (eds) Automata Studies. Princeton Univ. Press, Princeton, NJ, pp 43–98
Wang A, Chandrakasan A (2005) A 180-mV subthreshold FFT processor using a minimum energy design methodology. IEEE J Solid-State Circuits 40(1):310–319, January
Weste N, Harris D (2004) CMOS VLSI design—a circuits and systems perspective, 3rd edn. Addison-Wesley
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Granhaug, K., Aunet, S. Improving Yield and Defect Tolerance in Subthreshold CMOS Through Output-Wired Redundancy. J Electron Test 24, 157–163 (2008). https://doi.org/10.1007/s10836-007-5027-1
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DOI: https://doi.org/10.1007/s10836-007-5027-1