Test Development Through Defect and Test Escape Level Estimation for Data Converters
- 76 Downloads
Testing integrated circuits (ICs) is understood as the task of filtering out defective ICs that violate data sheet specifications. The costs of this filter comprise both the direct cost of testing a device and the indirect cost of test escapes and test yield–loss. For analog and mixed-signal devices, such as data converters, traditional methods of estimating the defect and test escape levels require large sample sets of devices. This is because the defect level induced by manufacturing process variations is typically low. In this work, a model-based method of estimating defect and test escape levels is described. For this method, a small set of sample devices is sufficient, as we first derive a manufacturing process model which is then used to simulate the manufacturing of a large number of devices. These simulation results are subsequently used for the purposes of estimating the defect and test escape levels, as well as the test-related yield–loss when applying a given test. With these estimates, the quality and indirect costs of a test can be determined as a function of the test limits and guard-bands applied in production test.
Keywordsmixed-signal and analog test economics of test test and post-test data analysis
Unable to display preview. Download preview PDF.
- 1.M.L. Abell, J.P. Braselton, and J.A. Rafter, Statistics with Mathematica, Academic, 1998.Google Scholar
- 2.P. Billingsley, Probability and Measure, 3rd. edition, Wiley, 1995.Google Scholar
- 3.M. Burns and G.W. Roberts, An Introduction to Mixed-Signal IC Test and Measurement, Oxford Series in Electrical and Computer Engineering, 1st edition, New York: Oxford University Press, 2001.Google Scholar
- 5.G. Gielen, G. Debyser, F. Leyn, and W. Sansen, “Efficient yield estimation within automated analog IC design,” In Proc. IWSM, Int. Workshop on Statistical Metrology, pp. 118–121, Honolulu, Hawaii USA, June 1998.Google Scholar
- 7.The Institute of Electrical and Electronics Engineers, Inc., New York. IEEE Std 1241-2000, IEEE standard for terminology and test methods for analog-to-digital converters, December 2000.Google Scholar
- 8.M. Li and L. Milor, “Computing Parametric Yield Using Adaptive Statistical Piecewise Linear Models,” In Proc. ISCAS, volume 4 of International. Symposium on Circuits and Systems, pp. 473–476, May 1996.Google Scholar
- 9.S. Mourad and Y. Zorian, Principles of Testing Electronic Systems, A Wiley-Interscience Publication, New York: Wiley, 2000.Google Scholar
- 10.T.M. Souders and G.N. Stenbakken, “Cutting the High Costs of Testing,” IEEE Spectrum, pp. 48–51, March 1991.Google Scholar
- 12.S. Sunter and N. Nagi, “Test Metrics for Analog Parametric Faults,” In Proc. VTS, VLSI Test Symposium, pp. 226–234, Dana Point, CA, USA, April 1999.Google Scholar
- 13.C. Wegener, Applications of Linear Modeling to Testing and Characterizing D/A and A/D Converters, PhD thesis, University College Cork, Dept. Microelectr. Eng., November 2003.Google Scholar
- 15.R.H. Williams and C.F. Hawkins, “The Economics of Guardband Placement,” In Proc. ITC, International Test Conference, pp. 218–224, 1993.Google Scholar