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Journal of Computational Electronics

, Volume 17, Issue 2, pp 646–652 | Cite as

Investigation of a novel SOI LDMOS using p+ buried islands in the drift region by numerical simulations

  • Jianmei Lei
  • Shengdong Hu
  • Dong Yang
  • Ye Huang
  • Qi Yuan
  • Jingwei Guo
  • Linghui Zeng
  • Siqi Wang
  • Xuan Yang
Article
  • 111 Downloads

Abstract

A novel SOI LDMOS with p+ buried islands and p-top layer in the drift region (PBI SOI) is proposed in this letter. At off-state, the high potential is induced from the drain region to the inside of the drift region. The p+ buried islands cause reduced surface field effect and modulate the electric field distribution in the drift region. The buried p-top layer withstands the lateral drain voltage. Thus, the breakdown voltage (BV) of PBI SOI is significantly improved. Meanwhile, the specific on-resistance \((R_\mathrm{on,sp})\) is reduced by improving doping concentration of the drift region, owing to the assisting depletion effect caused by the p+ buried islands. Consequently, the \(R_\mathrm{on,sp}\) of the proposed structure is reduced by 53.7% compared with the conventional SOI LDMOS at the same half-pitch size, the BV and the figure-of-merit \((\hbox {FOM} = \hbox {BV}^{2}/ R_\mathrm{on,sp})\) are observably improved by 24.8% and 235.9% respectively.

Keywords

SOI LDMOS Breakdown voltage Specific on-resistance RESURF p\(^{+}\) buried island 

Notes

Acknowledgements

This work is supported by the National Natural Science Foundation of China (Grant No. 61574023), the Open Funds of State Key Laboratory of Vehicle NVH and Safety Technology (Grant Nos. NVHSKL-201414 and 201608), and Innovative support program for returned overseas students in Chongqing (Grant No. cx2017009) and Chongqing Key R&D Project (Grant No. cstc2017zdcy-zdyfx0090).

References

  1. 1.
    Stork, M.C.Johannes, Hosey, G.P.: SOI technology for power management in automotive and industrial applications. Solid State Electron. 128, 3–9 (2017)CrossRefGoogle Scholar
  2. 2.
    Udrea, F., Garner, D., Sheng, K., et al.: SOI power devices. Electron. Commun. Eng. J. 12(1), 27–40 (2000)CrossRefGoogle Scholar
  3. 3.
    Cheng, K., Hu, s, Jiang, Y., Yuan, Q., Yang, Dong, Huang, Y., Mei, L., Lin, Z., Zhou, X., Tang, F.: Simulation-based performance analysis of an ultra-low specific on-resistance trench SOI LDMOS with a floating vertical field plate. J. Comput. Electron. 16(1), 83–89 (2017)CrossRefGoogle Scholar
  4. 4.
    Zareiee, M., Orouji, A.A., Mehrad, M.: A novel high breakdown voltage LDMOS by protruded silicon dioxide at the drift region. J. Comput. Electron. 15(2), 611–618 (2016)CrossRefGoogle Scholar
  5. 5.
    Zareiee, M.: Modifying buried layers in nano-MOSFET for achieving reliable electrical characteristics. ECS J. Solid State Sci. Technol. 5(10), M113–M117 (2016)CrossRefGoogle Scholar
  6. 6.
    Zareiee, M., Mehrad, M.: A reliable nano device with appropriate performance in high temperatures. ECS J. Solid State Sci. Technol. 6(4), M50–M54 (2017)CrossRefGoogle Scholar
  7. 7.
    Orouji, A.A., Mehrad, M.: Breakdown voltage improvement of LDMOSs by charge balancing: an inserted P-layer in trench oxide (IPT-LDMOS). Superlattices Microstruct. 51(3), 412–420 (2012)CrossRefGoogle Scholar
  8. 8.
    Mehrad, M., Orouji, A.A., Taheri, M.: A new technique in LDMOS transistors to improve the breakdown voltage and the lattice temperature. Mater. Sci. Semicond. Process. 34, 276–280 (2015)CrossRefGoogle Scholar
  9. 9.
    Hu, X.R., Zhang, B., Luo, X.R., Liang, Y.G., Chen, X., Li, Z.J.: A new high voltage SOI LDMOS with triple RESURF structure. J. Semicond. 32(7), 1–4 (2011)Google Scholar
  10. 10.
    Orouji, A.A., Rahimifar, A., Jozi, M.: A novel double-gate SOI MOSFET to improve the floating body effect by dual SiGe trench. J. Comput. Electron. 15(2), 537–544 (2016)CrossRefGoogle Scholar
  11. 11.
    Chen, Y.H., Hu, S.D., Cheng, K., Jiang, Y.Y., Zhou, J.L., Tang, F., Zhou, X.C., Gan, P.: Improving breakdown performance for novel LDMOS using \(n^{+}\) floating islands in substrate. Electron. Lett. 52(8), 658–659 (2016)CrossRefGoogle Scholar
  12. 12.
    Son, W.S., Sohn, Y.H., Choi, S.Y.: RESURF LDMOSFET with a trench for SOI power integrated circuits. Microelectron. J. 35(5), 393–400 (2004)CrossRefGoogle Scholar
  13. 13.
    Hardikar, S., Souza, M.M.D., Xu, Y.Z., et al.: A novel double RESURF LDMOS for HVIC’s. Microelectron. J. 35(3), 305–310 (2004)CrossRefGoogle Scholar
  14. 14.
    Han, S.Y., Kim, H.W., Chung, S.K.: Surface field distribution and breakdown voltage of RESURF LDMOSFETs. Microelectron. J. 31(8), 685–688 (2000)CrossRefGoogle Scholar
  15. 15.
    Taurus-MEDICI User Guide. Version D-2010.03, Synopsys, Mountain View, CA, USA, Mar. (2010)Google Scholar
  16. 16.
    Hu, Y., Huang, Q.J., Wang, G.F.: A novel high-voltage(\(> 600 \text{ V }\)) LDMOSFET with buried N-Layer in partial SOI technology. IEEE Trans. Electron Devices 59(4), 1131–1136 (2012)CrossRefGoogle Scholar
  17. 17.
    Luo, X.R., Li, Z.J., Zhang, B.: Realization of high voltage(\(> 700 \text{ V }\)) in new SOI devices with a compound buried layer. IEEE Electron Device Lett. 29(12), 1395–1397 (2008)CrossRefGoogle Scholar
  18. 18.
    Luo, X.R., Zhang, B., Li, Z.J.: A novel 700-V SOI LDMOS with double-sided trench. IEEE Electron Device Lett. 28(5), 422–424 (2007)CrossRefGoogle Scholar
  19. 19.
    Roig, J., Flores, D., Hidalgo, S., et al.: Study of novel techniques for reducing self-heating effects in SOI power LDMOS. Solid State Electron. 46(12), 2123–2133 (2002)CrossRefGoogle Scholar
  20. 20.
    Lun, Z., Du. G., Qin, J., et al: Investigation of self-heating effect in SOI-LDMOS by device simulation. In: IEEE International Conference on Solid-State and Integrated Circuit Technology, pp. 1–3 (2012)Google Scholar
  21. 21.
    Jiang, L.: Hot carrier effect on LDMOS transistors. Dissertation for the degree of Doctor of Philosophy (2007)Google Scholar
  22. 22.
    Wang, C.: Hot Carrier Design Considerations for MOS Devices and Circuits, pp. 250–310. Springer, Berlin (1992)CrossRefGoogle Scholar
  23. 23.
    Shahabuddin, S., Goh, K.K., Goh, K.K., et al.: Voltage dependences of parameter drifts in hot carrier degradation for n-channel LDMOS transistor. Microelectron. Eng. 109(C), 101–104 (2013)CrossRefGoogle Scholar
  24. 24.
    Wei, J., Zhang, C., Liu, S., et al.: Investigation on Hot-Carrier-Induced degradation of STI-nLDMOS with two-step-oxide process for high side application. In: International Symposium on Power Semiconductor Devices and ICS, pp. 383–386. IEEE (2016)Google Scholar
  25. 25.
    Liu, S., Li, S., Li, Z., et al.: Lateral DMOS with partial-resist-implanted drift region for alleviating hot-carrier effect. IEEE Trans. Device Mater. Reliab. 99, 1–1 (2017)Google Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.State Key Laboratory of Vehicle NVH and Safety TechnologyChina Automotive Engineering Research Institute Co. Ltd.ChongqingChina
  2. 2.Key Laboratory of Dependable Service Computing in Cyber Physical Society, Ministry of Education, and Chongqing Engineering Laboratory of High Performance Integrated Circuits, College of Communication EngineeringChongqing UniversityChongqingChina

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