Advertisement

Journal of Computational Electronics

, Volume 17, Issue 3, pp 1210–1219 | Cite as

High electric field stress model of n-channel VDMOSFET based on artificial neural network

  • Sanja Aleksić
  • Aleksandar Pantić
  • Dragan Pantić
Article
  • 47 Downloads

Abstract

In VDMOSFETs (Vertical Double-Diffused Metal-Oxide Semiconductor Field-Effect Transistor), in the cases when the voltage at the gate contact comes close to the breakdown voltage, a high electric field (HEF) is formed in the gate oxide. This leads to the generation of fixed and mobile charged defects in the gate oxide and at the silicon/oxide interface. The mechanisms of defects formation are very complex, so it is impossible to create a unique physical model that could describe the behavior of components, i.e., its electrical characteristics, depending on the stress voltage and the stress time. In cases like this, the application of artificial neural network (ANN) has proved to be one of the acceptable solution. In fact, this approach can give the very accurate models for the define range of changes of the input parameters, without going into very complex physical and chemical processes that occur in the structure of the components. All that is necessary to generate the ANN model is the sufficiently large number of the measured data and correct selection of the neural network structure and appropriate training algorithm. In this paper, we have applied the multilayer feedforward neural networks to the model of high electric field stress effects (HEFS) in the n-channel VDMOS power transistor. Experimentally measured transfer characteristics for different times of stress were used to train the neural networks of different configurations. In addition, the influence of several different training algorithms on the accuracy of the model was studied. It is shown that a properly selected neural network structure and training algorithm provide the ANN model of HEFS of the n-channel VDMOS power transistor that very precisely gives its electrical characteristics (transfer characteristic and threshold voltage) for a given stress voltage and temperature in the whole range of the time stress changes from 0 to 150 min.

Keywords

Neural network Model High electric field stress VDMOSFET Simulation 

Notes

Acknowledgements

This work has been supported by the Ministry of Education and Science of the Republic of Serbia, under the Project TR 33035.

References

  1. 1.
    DiMaria, D.J., Stasiak, J.W.: Trap creation in silicon dioxide produced by hot electrons. J. Appl. Phys. 65, 2342–2346 (1989)CrossRefGoogle Scholar
  2. 2.
    Wang, T., Chiang, L., Zous, N., Chang, T., Huang, C.: Characterization of various stress-induced oxide traps in MOSFETs by using a subthreshold transient current technique. IEEE Trans. Electron Dev. 45(8), 1791–1796 (1998)CrossRefGoogle Scholar
  3. 3.
    Jakšić, A., Pejović, M., Ristić, G., Raković, S.: Latent interface-trap generation in commercial power VDMOSFETs. IEEE Trans. Nucl. Sci. 45(3), 1365 (1998)CrossRefGoogle Scholar
  4. 4.
    Stojadinović, N., et al.: Effects of electrical stressing in power VDMOSFETs. Microelectron. Reliab. 45, 115–122 (2005)Google Scholar
  5. 5.
    Ristić, G., Pejović, M., Jakšić, A.: Fowler–Nordheim high electric field stress of power VDMOSFETs. Solid State Electron. 49, 1140–11152 (2005)CrossRefGoogle Scholar
  6. 6.
    Alwan, M., Beydoun, B., Ketata, K., Zoaeter, M.: Bias temperature instability from gate charge characteristics investigations in n-channel power MOSFET. Microelectron. J. 38, 727–734 (2007)CrossRefGoogle Scholar
  7. 7.
    Aleksić, S., Jakšić, A., Pejović, M.: Repeating of positive and negative high electric field stress and corresponding thermal post-stress annealing of the n-channel power VDMOSFETs. Solid State Electron. 52(8), 1197 (2008)CrossRefGoogle Scholar
  8. 8.
    Guerin, C., Huard, V., Bravaix, A.: General framework about defect creation at the Si/SiO\(_{2}\) interface. J. Appl. Phys. 105(11), 114513 (2009)CrossRefGoogle Scholar
  9. 9.
    Schanovsky, F., Gös, W., Grasser, T.: An advanced description of oxide traps in MOS transistors and its relation to DFT. J. Comput. Electron. 9, 135 (2010).  https://doi.org/10.1007/s10825-010-0323-x CrossRefGoogle Scholar
  10. 10.
    Aleksić, S., Pantić, D., Pantić, D.: The influence of interface and semiconductor bulk traps generated under HEFS on MOSFETs electrical characteristics. In: Proceedings of 5th Small System Simulation Symposium (2014)Google Scholar
  11. 11.
    Alam, M.A., Mahapatra, S.: A comprehensive model of PMOS NBTI degradation. Microelectron. Reliab. 45, 71 (2005)CrossRefGoogle Scholar
  12. 12.
    Kufluoglu, H., Alam, M.A.: A generalized reaction–diffusion model with explicit H–H\(_{2}\) dynamics for negative-bias temperature-instability (NBTI) degradation. IEEE Trans. Electron Dev. 54, 1101 (2007)CrossRefGoogle Scholar
  13. 13.
    Maiti, T.K., Mahato, S.S., Chakraborty, P., et al.: Negative bias temperature instability in strain-engineered p-MOSFETs: a simulation study. J. Comput. Electron. (2010).  https://doi.org/10.1007/s10825-009-0270-6 Google Scholar
  14. 14.
    Aleksić, S., Pešić, B., Pantić, D.: Simulation of bulk traps influence on the electrical characteristics of VDMOS transistor. In: XLVI International Scientific Conference on Information, Communication and Energy Systems and Technologies (ICEST), p. 271 (2011)Google Scholar
  15. 15.
    Aleksić, S., Peić, B., Pantić, D.: Simulation of semi-conductor bulk trap influence on the electrical characteristics of the n-channel power VDMOS transistor. Inf. MIDEM 43(2), 124–130 (2013)Google Scholar
  16. 16.
    Hagan, M.T., Demuth, H.B., Beale, M.H., Jesus, O.D.: Neural Network Design, 2nd edn. PWS Publication, Boston (2014)Google Scholar
  17. 17.
    Pantić, D., Trajković, T., Milenković, S., Stojadinović, N.: Optimization of power VDMOSFET’s process parameters by neural networks. In: Proceedings on 25th European Solid State Device Research Conference (ESSDERC’95), pp. 793–796 (1995)Google Scholar
  18. 18.
    Pantić, D., Trajković, S., Stojadinović, N.: A new technology computer-aided design (TCAD) system based on neural network models. Microelectron. J. 29, 1–4 (1998)CrossRefGoogle Scholar
  19. 19.
    Caddemi, A., Donato, N., Xibilia, M.: Advanced simulation of semiconductor devices by artificial neural network. J. Comput. Electron. 2, 301 (2003).  https://doi.org/10.1023/B:JCEL.0000011442.17774.cf CrossRefGoogle Scholar
  20. 20.
    Vulović, A., Savić, M., Aleksić, S., Pantić, D.: ANN model of high electric field stress in n-channel VDMOS power transistor. In: Proceedings of 5th Small System Simulation Symposium (2016)Google Scholar
  21. 21.
    Zhang, L., Chan, M.: Artificial neural network design for compact modeling of generic transistors. J. Comput. Electron. (2017).  https://doi.org/10.1007/s10825-017-0984-9 Google Scholar
  22. 22.
    MATLAB and Neural Network Toolbox Release 2018a. The MathWorks Inc., Natick, MA (2018)Google Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Faculty of Electronic EngineeringUniversity of NišNišSerbia
  2. 2.Inovation Center of Advanced TechnologyNišSerbia

Personalised recommendations