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Analysis and modeling of unipolar junction transistor with excellent performance: a novel DG MOSFET with \({N}^{+}{-}{P}^{-}\) junction

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Abstract

We propose herein a new dual-gate metal–oxide–semiconductor field-effect transistor (MOSFET) with just a unipolar junction (UJ-DG MOSFET) on the source side. The UJ-DG MOSFET structure is constructed from an \({N}^{+}\) region on the source side with the rest consisting of a \({P}^{-}\) region over the gate and drain, forming an auxiliary gate over the drain region with appropriate length and work function (named A-gate), converting the drain to an \({N}^{+}\) region. The new structure behaves as a MOSFET, exhibiting better efficiency than the conventional double-gate MOSFET (C-DG MOSFET) thanks to the modified electric field. The amended electric field offers advantages including improved electrical characteristics, reliability, leakage current, \({I}_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio, gate-induced drain leakage, and electron temperature. Two-dimensional analytical models of the surface potential and electric field over the channel and drain are applied to investigate the drain current in the UJ-DG MOSFET. To confirm their accuracy, the MOSFET characteristics obtained using the 2D Atlas simulator for the UJ-DG and C-DG are analyzed and compared.

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References

  1. Ghosh, B., Waseem Akram, M.: Junctionless tunnel field effect transistor. IEEE Electron Device Lett. 34(5), 584–586 (2013)

    Article  Google Scholar 

  2. Gundapaneni, S., Bajaj, M., Pandey, R.K., Murali, K.V.R., Ganguly, S., Kottantharayil, A.: Effect of band-to-band tunneling on junctionless transistors. IEEE Trans. Electron Devices 59(4), 1023–1029 (2012)

    Article  Google Scholar 

  3. Ramezani, Zeinab, Orouji, A.A.: Investigation of vertical graded channel doping in nanoscale fully-depleted SOI-MOSFET. Superlattices Microstruct. 98, 359–370 (2016)

    Article  Google Scholar 

  4. Chopra, M., Gill, N., Singh, H.: Performance analysis of full adder circuit using double gate MOSFET. Int. J. Comput. Appl. 129(12), 28–33 (2015)

    Google Scholar 

  5. Navya Sri, K., Lingaiah, J.: Design of full adder circuit using double gate MOSFET. Int. J. Adv. Technol. Innov. Res. 8(18), 3579–3582 (2016)

    Google Scholar 

  6. Alioto, M., Palumbon, G.: Analysis and comparison on full adder block in submicron technology. IEEE Trans. Very Large Scale Integr. VLSI Syst. 10(6), 806–823 (2002)

    Article  Google Scholar 

  7. Sharma, R., Pandey, S., Jain, S.B.: Analytical modeling of drain current and RF performance for double-gate fully depleted nanoscale SOI MOSFETs. J. Semicond. 33(2), 024001 (2012)

    Article  Google Scholar 

  8. Vishnoi, R., Kumar, M.J.: A pseudo 2D-analytical model of dual material gate all-around nanowire tunneling FET. IEEE Trans. Electron Devices 61, 2264–2270 (2014)

    Article  Google Scholar 

  9. Rahimian, M., Fathipour, M.: Asymmetric junctionless nanowire TFET with built-in \(n^{+}\) source pocket emphasizing on energy band modification. J. Comput. Electron. 15(4), 1297–1307 (2016)

    Article  Google Scholar 

  10. Kumar, M.J., Janardhanan, S.: Doping-less tunnel field effect transistor: design and investigation. IEEE Trans. Electron Devices 60(10), 3285–3290 (2013)

    Article  Google Scholar 

  11. Rajasekharan, B., Hueting, R.J.E., Salm, C., van Hemert, T., Wolters, R.A.M., Schmitz, J.: Fabrication and characterization of the charge-plasma diode. IEEE Electron Device Lett. 31(6), 528–530 (2010)

    Article  Google Scholar 

  12. Hueting, R.J.E., Rajasekharan, B., Salm, C., Schmitz, J.: Charge plasma p-n diode. IEEE Electron Device Lett. 29(12), 1367–1368 (2008)

    Article  Google Scholar 

  13. Kumar, M.J., Nadda, K.: Bipolar charge plasma transistor: a novel three terminal device. IEEE Trans. Electron Devices 59(4), 962–967 (2012)

    Article  Google Scholar 

  14. Nadda, K., Kumar, M.J.: Schottky collector bipolar transistor without impurity doped emitter and base: design and performance. IEEE Trans. Electron Devices 60(9), 2956–2959 (2013)

    Article  Google Scholar 

  15. Nikoli, M.V., Radi, S.M., Mini, V., Risti, M.M.: The dependence of the work function of rare earth metals on their electron structure. Microelectron. J. 27, 93–96 (1996)

    Article  Google Scholar 

  16. Rahimian, M., Fathipour, M.: Improvement of electrical performance in junctionless nanowire TFET using hetero-gate-dielectric. Mater. Sci. Semicond. Process. 63, 142–152 (2017)

    Article  Google Scholar 

  17. Abadi, R.M.I., Ziabari, S.A.S.: Representation of type I heterostructure junctionless tunnel field effect transistor for high-performance logic application. Appl. Phys. A 122, 616 (2016)

    Article  Google Scholar 

  18. Device simulator Atlas: Atlas User’s Manual, Silvaco International Software, Santa Clara, CA, USA (2015)

  19. Asthana, P.K., Ghosh, B., Goswami, Y., Tripathi, B.M.M.: High-speed and low-power ultradeep-submicrometer III–V heterojunctionless tunnel field-effect transistor. IEEE Trans. Electron Devices 61(2), 479–485 (2014)

    Article  Google Scholar 

  20. Ramezani, Z., Orouji, Ali A.: Investigation of vertical graded channel doping in nanoscale fully-depleted SOI-MOSFET. Superlattices Microstruct. 98, 359–370 (2016)

    Article  Google Scholar 

  21. Ramezani, Z., Orouji, A.A.: Amended electric field distribution: a reliable technique for electrical performance improvement in nano scale SOI MOSFETs. J. Electron. Mater. 46(4), 2269–2281 (2017)

    Article  Google Scholar 

  22. Rama, M.S., Abdi, D.B.: Dopingless PNPN tunnel FET with improved performance: design and analysis. Superlattices Microstruct. 82, 430–437 (2015)

    Article  Google Scholar 

  23. Abdi, D.B., Kumar, M.J.: PNPN tunnel FET with controllable drain side tunnel barrier width: proposal and analysis. Superlattices Microstruct. 86, 121–125 (2015)

    Article  Google Scholar 

  24. Chen, J., Chan, T.Y., Chen, I.C., Ko, P.K., Hu, C.: Subbreakdown drain leakage current in MOSFET. IEEE Electron Device Lett. EDL–8, 515–517 (1987)

    Article  Google Scholar 

  25. Chan, T.Y., Chen, J., Ko, P.K., Hu, C.: The impact of gate-drain leakage current on MOSFET Scaling. In: IEDM Technical Digest, p. 718 (1987)

  26. Schwerin, A.V., Bergner, W.: Simulation of amplified gat-induced-drain-leakage (GIDL) in short-channel SOI MOSFETs. IEEE, pp. 7–10 (1994)

  27. Yuan, X., Park, J.-E., Wang, J., Zhao, E.: Characterization and analysis of gate-induced-drain-leakage current in 45 nm CMOS technology. In: IEEE International Integrated Reliability Workshop Final Report, pp. 70 – 73 (2007)

  28. Banerjee, S., Coleman, J., Richardson, B., Shah, A.: A band-to-band tunneling effect in the trench transistor cell. In: Proceedings of VLSI Symposia, pp. 97–98 (1987)

  29. Risch, L., Maly, R., Berger, W., Kirchen, R.: Charge losses of n-doped trench cells. In: Proceedings of Solid State Devices and Materials, pp. 585–588 (1988)

  30. Gnani, E., Gnudi, A., Reggiani, S., Baccarani, G.: Physical model of the junctionless UTB SOI-FET. IEEE Trans. Electron Device 59, 941–948 (2012)

    Article  Google Scholar 

  31. Parihar, M.S., Ghosh, D., Kranti, Abhinav: Ultra low power junctionless MOSFETs for subthreshold logic applications. IEEE Trans. Electron Devices 60(5), 1540–1545 (2013)

    Article  Google Scholar 

  32. Dasgupta, A., Das, R., Dutta, A., Kundu, A., Sarkar, C.K.: A comparative study of analog/RF performance: symmetric and asymmetric underlap gate stack DG-MOSFETs. In: Third International Conference on Devices, Circuits and Systems, pp. 148–151 (2016)

  33. Ramezani, Zeinab, Orouji, Ali A., Rahimian, Morteza: High-performance SOI MESFET by modified depletion region using a triple recessed gate. Mater. Sci. Semicond. Process. 30, 75–84 (2015)

    Article  Google Scholar 

  34. Sivilicic, B., Jovanovic, V., Suligoj, T.: Analytical models of front and back-gate potential distribution and threshold voltage for recessed source/drain UTB SOI MOSFETs. Solid State Electron 53, 540–547 (2009)

    Article  Google Scholar 

  35. Pandey, M.K., Sen, S., Gupta, R.S.: Thermal characterization of double-gate silicon-on-insulator MOSFET. J. Phys. D Appl. Phys. 32, 344 (1999)

    Article  Google Scholar 

  36. Kane, E.O.: Zener tunneling in semiconductors. J. Phys. Chem. Solids 12(2), 181–188 (1960)

    Article  Google Scholar 

  37. Gholizadeh, M., Hosseini, S.E.: A 2-D analytical model for double gate tunnel FETs. IEEE Trans. Electron Devices 61(5), 1494–1500 (2014)

    Article  Google Scholar 

  38. Toh, E.H., Wang, G.H., Chan, L., Samudra, G., Yeo, Y.C.: Device physics and guiding principles for the design of double-gate tunneling field effect transistor with silicon-germanium source heterojunction. Appl. Phys. Lett. 91, 243505 (2007)

    Article  Google Scholar 

Download references

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Correspondence to Ali A. Orouji.

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Ramezani, Z., Orouji, A.A. Analysis and modeling of unipolar junction transistor with excellent performance: a novel DG MOSFET with \({N}^{+}{-}{P}^{-}\) junction. J Comput Electron 17, 670–681 (2018). https://doi.org/10.1007/s10825-018-1152-6

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