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Stochastic circuit breaker network model for bipolar resistance switching memories

  • S.I.: Computational Electronics of Emerging Memory Elements
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Abstract

We present a stochastic model for resistance switching devices in which a square grid of resistor breakers plays the role of the insulator switching layer. The probability of breaker switching between two fixed resistance values, \(R_\mathrm{OFF}\) and \(R_\mathrm{ON}\), is determined by the corresponding voltage drop and thermal Joule heating. The breaker switching produces the overall device resistance change. Salient features of all the switching operations of bipolar resistance switching memories (RRAMs) are reproduced by the model and compared to a prototypical \(\hbox {HfO}_2\)-based RRAM device. In particular, the need of a forming process that leads a fresh highly insulating device to a low resistance state (LRS) is captured by the model. Moreover, the model is able to reproduce the RESET process, which partially restores the insulating state through a gradual resistance transition as a function of the applied voltage and the abrupt nature of the SET process that restores the LRS. Furthermore, the multilevel capacity of a typical RRAM device obtained by tuning RESET voltage and SET compliance current is reproduced. The manuscript analyses the peculiar ingredients of the model and their influence on the simulated current–voltage curves and, in addition, provides a detailed description of the mechanisms that connect the switching of the single breakers and that of the overall device.

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Notes

  1. the fraction of breaker is evaluated with respect of the total amount of breakers in the grid, i.e., \((m-1)\cdot n\) vertical and \(m\cdot (n-1)\) horizontal breakers.

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Acknowledgements

The work is partially supported by the European Project H2020-ICT-2015 NEUral computing aRchitectures in Advanced Monolithic 3D-VLSI nano-technologies (\(\hbox {NEURAM}^3\), Grant Agreement No. 687299).

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Brivio, S., Spiga, S. Stochastic circuit breaker network model for bipolar resistance switching memories. J Comput Electron 16, 1154–1166 (2017). https://doi.org/10.1007/s10825-017-1055-y

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