Abstract
In this paper, analytical subthreshold current and subthreshold swing models are derived for the short-channel dual-metal-gate (DMG) fully-depleted (FD) recessed-source/ drain (Re-S/D) SOI MOSFETs considering that diffusion is the dominant current flow mechanism in subthreshold regime of the device operation. The two-dimensional (2D) channel potential is derived in terms of back surface potential and other device parameters. The so called virtual cathode potential in term of the minimum of back surface potential is also derived from 2D channel potential. The virtual cathode potential based subthreshold current and surface potential based subthreshold swing model results are extensively analyzed for various device parameters like the oxide and silicon thicknesses, thickness of source/drain extension in the BOX, control to screen gate length ratio and channel length. The numerical simulation results obtained from ATLAS\(^{\text{ TM }}\), a 2D numerical device simulator from SILVACO Inc have been used as a tool to verify the model results.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Iwai, H.: Roadmap for 22nm and beyond. Microelectron. Eng. 86, 1520–1528 (2009)
Fischetti, M.V.: Scaling MOSFETs to the limit: a physicists’s perspective. J. Compt. Electron. 2, 73–79 (2003)
The International Technology Roadmap for Semiconductors, 2011 Edition. International SEMATECH, Austin, TX (2011). http://www.itrs.net/Links/2011ITRS/Home2011.htm
Wann, C.H., Noda, K., Tanaka, T., Yoshida, M.: A comparative study of advanced MOSFET concepts. IEEE Trans. Electron Devices 43, 1742–1753 (1996)
Chang, L., Choi, Y.K., Ha, D., Ranade, P.: Extremely scaled silicon nano-CMOS devices. Proc. IEEE 91, 1860–1873 (2003)
Kumar, M.J., Chaudhry, A.: Two-dimensional analytical modeling of fully depleted DMG SOI MOSFET and evidence for diminished SCEs. IEEE Trans. Electron Devices 51, 569–574 (2004)
Balestra, F., Christoloveanu, S., Benachir, M., Brini, J.: Double-gate silicon-on-insulator transistor with volume inversion: a new device with greatly enhanced performance. IEEE Electron Device Lett. 8, 410–412 (1987)
Colinge, J.P.: Multi-gate SOI MOSFETs. Microelectron. Eng. 84, 2071–2076 (2007)
Zhang, Z., Zhang, S., Chan, M.: Self-align recessed source drain ultrathin body SOI MOSFET. IEEE Electron Device Lett. 25, 740–742 (2004)
Svilíc, B., Jovanović, V., Suligoj, T.: Analytical models of front- and back-gate potential distribution and threshold voltage for recessed source/drain UTB SOI MOSFETs. Solid-State Electron. 53, 540–547 (2009)
Svilíc, B., Jovanović, V., Suligoj, T.: Analysis of subthreshold conduction in short-channel recessed source/drain UTB SOI- MOSFETs. Solid-State Electron. 54, 545–551 (2010)
Long, W., Ou, H., Kuo, J.M., Chin, K.K.: Dual-material gate (DMG) field effect transistor. IEEE Trans. Electron Devices 46, 865–870 (1999)
Reddy, G.V., Kumar, M.J.: A new dual-material double-gate (DMDG) nanoscale SOI MOSFET-two-dimensional analytical modeling and simulation. IEEE Trans. Nanotechnol. 4, 260–268 (2005)
Qiang, L., Ranade, P., Takeuchi, H., Yang, K.J., Polishchuk, I., Tsu- Jae, K., Chenming, H., Song, S.C., Luan, H.F., Lee, K.D.: Dual-metal gate CMOS technology with the ultrathin silicon nitride gate dielectric. IEEE Electron Device Lett. 22, 227–229 (2001)
Saramekala, G.K., Santra, A., Dubey, S., Jit, S., Tiwari, P.K.: An analytical threshold voltage model for a short-channel dual-metal-gate (DMG) fully depleted recessed-source/drain (Re-S/D) SOI MOSFET. Superlattices Microstruct. 60, 580–595 (2013)
Yeh, P.C., Fossum, J.G.: Physical subthreshold MOSFET modeling applied to viable design of deep-sub micrometer fully depleted SOI low-voltage CMOS Technology. IEEE Trans. Electron Devices 42, 1605–1613 (1995)
Yan, R.H., Ourmazd, A., Lee, K.F.: Scaling the Si MOSFET: from bulk to SOI to bulk. IEEE Trans. Electron Devices 39, 1605–1613 (1992)
Niu, G.F., Ruan, G.: An analytical back gate bias dependent subthreshold swing model for accumulation-mode P-channel SOI MOSFETs. Solid-State Electron. 38, 1805–1810 (1995)
Suzuki, K., Tanaka, T., Tosaka, Y., Horie, H., Arimoto, Y.: Scaling theory for double-gate SO1 MOSFET’s. IEEE Trans. Electron Devices 40, 2326–2329 (1993)
Dey, A., Chakravorty, A., DasGupta, N., DasGupta, A.: Analytical model of subthreshold current and slope for asymmetric 4-T and 3-T double- Gate MOSFETs. IEEE Trans. Electron Devices 55, 3442–3449 (2008)
Luan, S., Liu, H., Jia, R., Wang, J.: Two-dimensional subthreshold current model for dualmaterial gate SOI nMOSFETs with single halo. Front. Electr. Electron. Eng 4, 98–103 (2009)
Tiwari, P.K., Dubey, S., Singh, K., Jit, S.: Analytical modeling of subthreshold current and subthreshold swing of short-channel triple-material double-gate (TM-DG) MOSFETs. Superlattices Microstruct. 51, 715–724 (2012)
Young, K.K.: Short-channel effect in fully depleted SOI MOSFETs. IEEE Trans. Electron Devices 36, 399–402 (1989)
Kumar, M., Dubey, S., Tiwari, P.K., Jit, S.: Two-dimensional modeling of subthreshold current and the subthreshold swing of double-material-gate (DMG) strained-Si (s-Si) on SGOI MOSFETs. J. Comput. Electron. 12, 275–280 (2013)
ATLAS User’s Manual: Device Simulation Software. Silvaco International, Santa Clara, CA (2008)
Acknowledgments
One of the authors, Dr. P. K. Tiwari, acknowledges the financial support received from Science and Engineering Research Board (SERB), Department of Science and Technology, Ministry of Human Resource and Development, Government of India under young scientist scheme.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Saramekala, G.K., Santra, A., Kumar, M. et al. Analytical subthreshold current and subthreshold swing models of short-channel dual-metal-gate (DMG) fully-depleted recessed-source/drain (Re-S/D) SOI MOSFETs. J Comput Electron 13, 467–476 (2014). https://doi.org/10.1007/s10825-014-0557-0
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10825-014-0557-0