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New Design of Reversible Full Adder/Subtractor Using R Gate

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Abstract

Quantum computers require quantum processors. An important part of the processor of any computer is the arithmetic unit, which performs binary addition, subtraction, division and multiplication, however multiplication can be performed using repeated addition, while division can be performed using repeated subtraction. In this paper we present two designs using the reversible R3 gate to perform the quantum half adder/subtractor and the quantum full adder/subtractor. The proposed half adder/subtractor design can be used to perform different logical operations, such as AND, XOR, NAND, XNOR, NOT and copy of basis. The proposed design is compared with the other previous designs in terms of the number of gates used, the number of constant bits, the garbage bits, the quantum cost and the delay. The proposed designs are implemented and tested using GAP software.

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Authors and Affiliations

  1. Department of Mathematics and Computer Science, Faculty of Science, Alexandria University, Alexandria, Egypt

    Rasha Montaser & Ahmed Younes

  2. School of Computer Science, University of Birmingham, Birmingham, B15 2TT, UK

    Ahmed Younes

  3. University of Science and Technology, Zewail City of Science and Technology, Zewail, Egypt

    Mahmoud Abdel-Aty

  4. Department of Mathematics, Faculty of Science, Sohag University, Sohag, Egypt

    Mahmoud Abdel-Aty

Authors
  1. Rasha Montaser
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  2. Ahmed Younes
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  3. Mahmoud Abdel-Aty
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Correspondence to Rasha Montaser.

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Montaser, R., Younes, A. & Abdel-Aty, M. New Design of Reversible Full Adder/Subtractor Using R Gate. Int J Theor Phys 58, 167–183 (2019). https://doi.org/10.1007/s10773-018-3921-1

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  • DOI: https://doi.org/10.1007/s10773-018-3921-1

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