Advent in VLSI technology made digital signal processing to take over analog signal processing. Analog to digital converter plays a vital role in modern digital signal processing applications. Various signal processing applications incorporated sigma delta ADC among different analog to digital converters because of its digital dominant architecture. This paper presents the design of a low pass continuous time sigma delta analog to digital converter on-chip architecture with a very few passive components connected externally to FPGA suitable for signal processing applications, wireless application, sonar and radar beamforming. Schematic level architecture of high speed comparator working at a differential swing which is not allowed by FPGA standard differential pads is designed. By applying various differential swings at the input to LVPECL, the performance and power is analyzed. High performance comparator schematic is designed as on-chip continuous-time sigma-delta analog to digital converter architecture. SPICE simulations are carried out to verify the maximum input frequency for given RC values. Xilinx provided Spartan 6 I/O pad and package SPICE models are used. Power analysis is carried out with LVPECL logic family based differential buffers along with external RC circuit. The analog and digital sections simulations along with mixed signal simulations at different stages are performed. Power and performance analysis are carried out using h-Spice and questasim simulations. schematic level architecture of a high speed comparator at a differential swing of 1.65 ± 1.5 V which is not allowed by standard differential pads is designed. Analysis illustrates that proposed on-chip continuous-time sigma-delta analog to digital converter exhibits a sampling rate of 400 MHz designed with high speed comparator with varied differential swing. Power analysis resulted with 1.86 mW for an input signal of 1 MHz. Optimal filtering is achieved with total decimation of 400, out of which the decimation of 100 is achieved by CIC filter and PFIR filter achieves remaining decimation factor of 4. Output data rate of 1 MHz with a dynamic range of 72 dB is achieved with less bill of material that suites for signal processing applications.
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Vardhini, P.A.H., Makkena, M.L. Design and comparative analysis of on-chip sigma delta ADC for signal processing applications. Int J Speech Technol (2021). https://doi.org/10.1007/s10772-021-09800-8
- Sigma delta ADC
- Differential I/O
- Optimum filtering