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Adaptive Thread Scheduling in Chip Multiprocessors

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Abstract

The full potential of chip multiprocessors remains unexploited due to architecture oblivious thread schedulers employed in operating systems. We introduce an adaptive cache-hierarchy-aware scheduler that tries to schedule threads in a way that inter-thread contention is minimized. A novel multi-metric scoring scheme is used which specifies L1 cache access characteristics of threads. Scheduling decisions are made based on these multi-metric scores of threads.

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Authors and Affiliations

  1. Department of Electrical Engineering and Computer Science, University of Missouri, Columbia, MO, USA

    Ismail Akturk

  2. Department of Computer Engineering, Bilkent University, Ankara, Turkey

    Ozcan Ozturk

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  1. Ismail Akturk
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  2. Ozcan Ozturk
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Akturk, I., Ozturk, O. Adaptive Thread Scheduling in Chip Multiprocessors. Int J Parallel Prog 47, 1014–1044 (2019). https://doi.org/10.1007/s10766-019-00637-y

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