Multilevel Data Processing Using Parallel Algorithms for Analyzing Big Data in High-Performance Computing

Article
Part of the following topical collections:
  1. Special Issue on Programming Models and Algorithms for Data Analysis in HPC Systems

Abstract

The growing gap between users and the Big Data analytics requires innovative tools that address the challenges faced by big data volume, variety, and velocity. Therefore, it becomes computationally inefficient to analyze such massive volume of data. Moreover, advancements in the field of Big Data application and data science poses additional challenges, where High-Performance Computing solution has become a key issue and has attracted attention in recent years. However, these systems are either memoryless or computational inefficient. Therefore, keeping in view the aforementioned needs, there is a requirement for a system that can efficiently analyze a stream of Big Data within their requirements. Hence, this paper presents a system architecture that enhances the working of traditional MapReduce by incorporating parallel processing algorithm. Moreover, complete four-tier architecture is also proposed that efficiently aggregate the data, eliminate unnecessary data, and analyze the data by the proposed parallel processing algorithm. The proposed system architecture both read and writes operations that enhance the efficiency of the Input/Output operation. To check the efficiency of the proposed algorithms exploited in the proposed system architecture, we have implemented our proposed system using Hadoop and MapReduce. MapReduce is supported by a parallel algorithm that efficiently processes a huge volume of data sets. The system is implemented using MapReduce tool at the top of the Hadoop parallel nodes to generate and process graphs with near real-time. Moreover, the system is evaluated in terms of efficiency by considering the system throughput and processing time. The results show that the proposed system is more scalable and efficient.

Keywords

Big Data HPC Parallel Processing algorithm Four-tier system architecture 

Notes

Acknowledgements

This work is supported by BK21 Plus project (SW Human Resource Development Program for Supporting Smart Life) funded by the Ministry of Education, School of Computer Science and Engineering, Kyungpook National University, Korea (21A20131600005) and NRF Grant funded by the Korean Government (NRF-2015R1D1A1A01058171).

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Copyright information

© Springer Science+Business Media New York 2017

Authors and Affiliations

  1. 1.Department of Information and Communication EngineeringYeungnam UniversityGyeongbukRepublic of Korea
  2. 2.School of Computer Science and EngineeringKyungpook National UniversityDaeguRepublic of Korea
  3. 3.Department of Embedded Systems EngineeringIncheon National UniversityIncheonKorea

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