Wideband Matched CMOS LNA Design Using R-L-C Loading Network
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This paper proposes a new methodology for designing and analyzing wideband matched CMOS LNA with R-L-C loading network, where validity of this new approach is supported by the agreement between the simulated input impedance of the LNA and its calculated counterpart. To demonstrate its feasibility, two wideband matched LNA’s are designed using TSMC 0.18-μm RF-CMOS process. One is for 3–8 GHz application and the second one targets at 8–25 GHz frequency range. The measured results of both circuits will then be presented.
KeywordsWideband Input matching Low noise amplifier LNA
The authors are very grateful for the support of the National Chip Implementation Center (CIC), Hsinchu, Taiwan, R.O.C., for chip fabrication and high frequency measurement.
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