Design Automation for Embedded Systems

, Volume 10, Issue 4, pp 285–298 | Cite as

A methodology aimed at better integration of functional verification and RTL design

  • Karina R. G. da Silva
  • Elmar U. K. Melcher
  • Isaac Maia
  • Henrique do N. Cunha


The advent of new 65 nm/90 nm VLSI technology and SoC design methodologies has brought an explosive growth in the complexity of modern electronic circuits. As a result, functional verification has become the major bottleneck in any digital design flow. Thus, new methods for easier, faster and more reusable verification are required. This paper proposes a verification methodology (VeriSC2) that guides the implementation of working testbenches during hierarchical decomposition and refinement of the design, even before the RTL implementation starts. This approach uses the SystemC Verification Library (SCV), in a tool capable of automatically generating testbench templates. A case study from a MPEG-4 decoder design is used to show the effectiveness of this approach.


Functional verification Functional coverage Testbench VeriSC2 SystemC SCV 


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Copyright information

© Springer Science + Business Media, LLC 2006

Authors and Affiliations

  • Karina R. G. da Silva
    • 1
  • Elmar U. K. Melcher
    • 1
  • Isaac Maia
    • 1
  • Henrique do N. Cunha
    • 1
  1. 1.Federal University of Campina GrandeBodocongóBrazil

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