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A novel flip-flop based error free, area efficient and low power pipeline architecture for finite impulse recursive system

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Abstract

An error free, area efficient and low power pipeline architecture for finite impulse recursive signal processing system on chip (SOC) is proposed. The pipeline stage is implemented for the FIR filter which forms the signal conditioning block of the SOC in 60 and 90 nm technology. The design, implementation and testing is performed using Altera Quartus 9.1, cyclone device family for 60 and 90 nm technology. The pipelining is designed with 3 and 5 stages. The combinational block consists of processing elements like array multiplier and ripple carry adder. The registers of the pipelining is designed using normal D flip-flop, Autogated and Razor flip-flop. The pipelining architecture is further extended towards shared component architecture. The proposed shared component architecture reduces the critical path, number of components by which area is reduced and power consumption. The proposed design reduces the error with fewer timing penalty. The results are compared with existing methods and the efficiency of proposed method is improved. The proposed flip flop is compared with the existing flip-flop and found that the static power consumption is reduced by 8% and dynamic power consumption by 56%. The proposed pipelined shared component architecture reduces the power consumption by 10% for static power and 75% for dynamic power. From the machine cycles execution analysis it is found that the proposed design saves clock cycles when an error occurs. When area is considered the proposed architecture contains less number of multipliers.

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References

  1. Myjak, M.J., Delgado-Frias, J.G., Jeon, S.K.: An energy-efficient differential flip-flop for deeply pipelined systems. Circuits Syst. 1, 203–207 (2003)

    Google Scholar 

  2. Kawaguchi, H., Sakurai, T.: A reduced clock-swing flip-flop (rcsff) for 63% power reduction. IEEE J. Solid State Circuits 33(5), 807–811 (1998)

    Article  Google Scholar 

  3. Lin, M.P.-H., Hsu, C.-C., Chen, Y.-C.: Clock-tree aware multi-bit flip-flop generation during placement for power optimization. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2013)

  4. Lin, J.-F.: Low-power pulse-triggered flip-flop design based on a signal feed-through scheme. IEEE Trans. VLSI Syst. 22(1), 181–185 (2014)

    Article  Google Scholar 

  5. Zhao, P., Mcneely, J.B., Golconda, P.K., Venigalla, S., Wang, N., Bayoumi, M.A., Kuang, W., Downey, L.: Low-power clocked-pseudo-nmos flip-flop forlevel conversion in dual supply systems. IEEE Trans. VLSI Syst. 17(9), 1196–1202 (2009)

    Article  Google Scholar 

  6. Tarawneh, G., Yakovlev, A., Mak, T.: Eliminating synchronization latency using sequenced latching. IEEE Trans. VLSI Syst. 22(2), 408–419 (2014)

    Article  Google Scholar 

  7. Chen, Y.-G., Geng, H., Lai, K.-Y., Shi, Y., Chang, S.-C.: Multibit retention registers for power gated designs: concept, design, and deployment. IEEE Trans. Comput. Aided Des. Integr Circuits Syst. 33(4), 517–518 (2014)

    Article  Google Scholar 

  8. Consoli, E., Palumbo, G., Rabaey, J.M., Alioto, M.: Novel class of energy-efficient very high-speed conditional push–pull pulsed latches. IEEE Trans. VLSI Syst. 22(7), 1593–1605 (2014)

    Article  Google Scholar 

  9. Shin, I., Kim, J.-J., Shin, Y.: Aggressive voltage scaling through fast correction of multiple errors with seamless pipeline operation. IEEE Trans. Circuits Syst. I 62(2), 468–477 (2015)

    Article  Google Scholar 

  10. Xia, Z., Hariyama, M., Kameyama, M.: Asynchronous domino logic pipeline design based on constructed critical data path. IEEE Trans. VLSI Syst. 23, 619–630 (2014)

    Article  Google Scholar 

  11. Chunhong, C., Changjun, K., Majid, S.: Activity-sensitive clock tree construction for low power. In: Proceedings of ISLPED, pp. 279–282 (2002)

  12. Farrahi, A., Chen, C., Srivastava, A., Tellez, G., Sarrafzadeh, M.: Activity—driven clock design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(6), 705–714 (2001)

    Article  Google Scholar 

  13. Shen, W., Cai, Y., Hong, X., Hu, J.: Activity and register placement aware gated clock network design. In: Proceedings of ISPD, pp. 182–189 (2008)

  14. Wimer, S., Koren, I.: The optimal fan-out of clock network for power minimization by adaptive gating. IEEE Trans. VLSI Syst. 20(10), 1772–1780 (2012)

    Article  Google Scholar 

  15. http://edu.cs.tut.fi/SA2007/EPs_pipe.html

  16. Raja, K., Saravanan, S., Anitha, R., Suganthi Priya, S., Subhashini, R.: Design of a low power ECG signal processor for wearable health system-review and implementation issues. In 2017 11th International Conference on Intelligent Systems and Control (ISCO), pp. 383–387. IEEE (2017)

  17. Raja, K., Saravanan, S., Malini, P., Raveena, V., Praveena, R.S.: Design of a spike detector for fully Integrated Neuromodulation SoC. In: 11th International Conference on Intelligent Systems and Control (ISCO), pp. 341–345. IEEE (2017)

  18. Raja, K., Saravanan, S.: A new clock gated flip flop for pipelining architecture. Circuits Syst. 7(08), 1361 (2016)

    Article  Google Scholar 

  19. Saravanan, S., Raja, K.: Shared processing element architecture for an area and power efficient FIR filter design using double base number system. Asian J. Res. Soc. Sci. Humanit. 6(8), 2513–2520 (2016)

    Google Scholar 

  20. Kumar, P.M., Gandhi, U., Varatharajan, R., Manogaran, G., Jidhesh, R., Vadivel, T.: Intelligent face recognition and navigation system using neural learning for smart security in Internet of Things. Cluster Comput. (2017). https://doi.org/10.1007/s10586-017-1323-4

    Article  Google Scholar 

  21. Gandhi, U.D., Kumar, P.M., Varatharajan, R., Manogaran, G., Sundarasekar, R., Kadu, S.: HIoTPOT: surveillance on IoT devices against recent threats. Wireless Pers. Commun. (2018). https://doi.org/10.1007/s11277-018-5307-3

    Article  Google Scholar 

  22. Manogaran, G., Lopez, D., Thota, C., Abbas, K.M., Pyne, S., Sundarasekar, R.: Big data analytics in healthcare Internet of Things. In: Innovative Healthcare Systems for the 21st Century, pp. 263–284. Springer International Publishing (2017)

  23. Varatharajan, R., Vasanth, K., Gunasekaran, M., Priyan, M., Gao, X.Z.: An adaptive decision based kriging interpolation algorithm for the removal of high density salt and pepper noise in images. Comp. Elect. Eng. (2017). https://doi.org/10.1016/j.compeleceng.2017.05.035

    Article  Google Scholar 

  24. Varatharajan, R., Manogaran, G., Priyan, M.K., Sundarasekar, R.: Wearable sensor devices for early detection of Alzheimer disease using dynamic time warping algorithm. Cluster Comput. (2017). https://doi.org/10.1007/s10586-017-0977-2

    Article  Google Scholar 

  25. Varatharajan, R., Manogaran, G., Priyan, M.K.: A big data classification approach using LDA with an enhanced SVM method for ECG signals in cloud computing. Multimed Tools Appl. (2017). https://doi.org/10.1007/s11042-017-5318-1

    Article  Google Scholar 

  26. Manogaran, G., Varatharajan, R., Lopez, D., Kumar, P.M., Sundarasekar, R., Thota, C.: A new architecture of Internet of Things and big data ecosystem for secured smart healthcare monitoring and alerting system. Future Gener Comp Syst. 82, 375–387 (2018). https://doi.org/10.1016/j.future.2017.10.045

    Article  Google Scholar 

  27. Thota, C., Sundarasekar, R., Manogaran, G., Varatharajan, R., Priyan, M.K.: Centralized fog computing security platform for IoT and cloud in healthcare system. In: Exploring the Convergence of Big Data and the Internet of Things, pp. 141–154. IGI Global (2018)

  28. Manogaran, G., Vijayakumar, V., Varatharajan, R., Kumar, P.M., Sundarasekar, R., Hsu, C.H.: Machine learning based big data processing framework for cancer diagnosis using hidden Markov Model and GM Clustering. Wireless Pers Commun. (2017). https://doi.org/10.1007/s11277-017-5044-z

    Article  Google Scholar 

  29. Manogaran, G., Thota, C., Lopez, D.: Human-computer interaction with big data analytics. In: HCI Challenges and Privacy Preservation in Big Data Security, pp. 1–22. IGI Global (2018)

  30. Manogaran, G., Varatharajan, R., Priyan, M.K.: Hybrid recommendation system for heart disease diagnosis based on multiple kernel learning with adaptive neuro-fuzzy inference system. Multimed Tools Appl. 77(4), 4379–4399 (2018). https://doi.org/10.1007/s11042-017-5515-y

    Article  Google Scholar 

  31. Varatharajan, R., Manogaran, G., Priyan, M.K., Balaş, V.E., Barna, C.: Visual analysis of geospatial habitat suitability model based on inverse distance weighting with paired comparison analysis. Multimed Tools Appl. (2017). https://doi.org/10.1007/s11042-017-4768-9

    Article  Google Scholar 

  32. Manickam, A., Devarasan, E., Manogaran, G., Priyan, M.K., Varatharajan, R., Hsu, C.H., Krishnamoorthi, R.: Score level based latent fingerprint enhancement and matching using SIFT feature. Multimed Tools Appl. (2018). https://doi.org/10.1007/s11042-018-5633-1

    Article  Google Scholar 

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Authors and Affiliations

  1. Department of ECE, CMR Engineering College, Kandlakoya Villaga, Hyderabad, Telangana, 501401, India

    Raja Krishnamoorthy

  2. Department of EEE, Muthayammal Engineering College, Rasipuram, Tamil Nadu, India

    S. Saravanan

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  1. Raja Krishnamoorthy
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  2. S. Saravanan
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Correspondence to Raja Krishnamoorthy.

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Krishnamoorthy, R., Saravanan, S. A novel flip-flop based error free, area efficient and low power pipeline architecture for finite impulse recursive system. Cluster Comput 22 (Suppl 6), 15137–15147 (2019). https://doi.org/10.1007/s10586-018-2513-4

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  • DOI: https://doi.org/10.1007/s10586-018-2513-4

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